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ST6209C Schematic ( PDF Datasheet ) - ST Microelectronics
| Teilenummer | ST6209C |
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| Beschreibung | (ST6208C - ST6220C) 8-BIT MCUs WITH A/D CONVERTER | |
| Hersteller | ST Microelectronics | |
| Logo |  |
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Gesamt 30 Seiten 
ST6208C/ST6209C
ST6210C/ST6220C
8-BIT MCUs WITH A/D CONVERTER,
TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
s Memories
– 1K, 2K or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
s Clock, Reset and Supply Management
– Enhanced reset system
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or
RC network, external clock, backup oscillator
(LFAO)
– Oscillator Safeguard (OSG)
– 2 Power Saving Modes: Wait and Stop
s Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 12 external interrupt lines (on 2 vectors)
s 12 I/O Ports
– 12 multifunctional bidirectional I/O lines
– 8 alternate function lines
– 4 high sink outputs (20mA)
s 2 Timers
– Configurable watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
s 1 Analog peripheral
– 8-bit ADC with 8 input channels (except on
ST6208C)
PDIP20
SO20
SSOP20
CDIP20W
(See Section 12.5 for Ordering Information)
s Instruction Set
– 8-bit data manipulation
– 40 basic instructions
– 9 addressing modes
– Bit manipulation
s Development Tools
– Full hardware/software development package
Device Summary
Features
ST62T08C(OTP)/
ST6208C(ROM)
ST62T09C(OTP)/
ST6209C (ROM)
ST62T10C(OTP)/
ST6210C (ROM)
ST62T20C(OTP)
ST6220C(ROM )
ST62E20C(EPROM)
ST62P08C(FASTROM) ST62P09C(FASTROM) ST62P10C(FASTROM) ST62P20C(FASTROM)
Program memory
- bytes
RAM - bytes
Operating Supply
Analog Inputs
Clock Frequency
Operating
Temperature
Packages
1K 2K 4K
64
3.0V to 6V
-4
8
8MHz Max
-40°C to +125°C
PDIP20/S O20/SSO P20
PDIP20/SO20
CDIP20W
Rev. 3.0
June 2000
1/105
1
 
ST6208C/ST6209C/ST6210C/ST6220C
1 INTRODUCTION
The ST6208C, 09C, 10C and 20C devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E20C is the erasable EPROM version of
the ST62T08C, T09C, T10C and T20C devices,
which may be used during the development phase
for the ST62T08C, T09C, T10C and T20C target
devices, as well as the respective ST6208C, 09C,
10C and 20C ROM devices.
OTP and EPROM devices are functionally identi-
cal. OTP devices offer all the advantages of user
programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
The ROM based versions offer the same function-
ality, selecting the options defined in the program-
Figure 1. Block Diagram
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 12.6 on page
96).
The ST62P08C/P09C/P10C/P20C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T08C, T09C, T10C and T20C
OTP devices.
They offer the same functionality as OTP devices,
but they do not have to be programmed by the
customer (See Section 12 on page 90).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable prescaler, an 8-bit A/D Converter with up to
8 analog inputs (depending on device) and a Dig-
ital Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
For easy reference, all parametric data are located
in Section 11 on page 62.
TEST/ VPP
NMI
TEST
INTERRUPTS
P:ROG RAM
MEMORY
(1K, 2K
or 4K Bytes)
8-BIT *
A/D CONVERTE R
DATA ROM
USER
S ELECTA BLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
PA0..PA3 (20mA Sink)
PB0..PB7 / Ain*
TIMER
PC
STAC K LEVEL 1
STAC K LEVEL 2
STAC K LEVEL 3
STAC K LEVEL 4
STAC K LEVEL 5
STAC K LEVEL 6
8-BIT CORE
POWE R
SU PPLY
O SCILLATO R
RE SET
VDDVSS OSCin OSCout RESET
* Depending on device. See device summary on page 1.
WATCHDOG
TIMER
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6 Page 
ST6208C/ST6209C/ST6210C/ST6220C
MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
080h
to 083h
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
CPU
I/O Ports
I/O Ports
X,Y, V,W
DRA 1) 2) 3)
DRB 1) 2) 3)
X,Y index registers
V,W short direct registers
Port A Data Register
Port B Data Register
DDRA 2)
DDRB 2)
Reserved (2 Bytes)
Port A Direction Register
Port B Direction Register
Reserved (2 Bytes)
xxh R/W
00h R/W
00h R/W
00h R/W
00h R/W
0C8h
0C9h
0CAh
0CBh
0CCh
0CDh
IOR
DRWR
I/O Ports
ORA 2)
ORB 2)
Interrupt Option Register
Data ROM Window register
Reserved (2 Bytes)
Port A Option Register
Port B Option Register
xxh Write-only
xxh Write-only
00h R/W
00h R/W
0CEh
0CFh
Reserved (2 bytes)
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
to 0D7h
0D8h
0D9h
to 0FEh
0FF
ADC 4)
Timer1
ADR
ADCR
PSCR
TCR
TSCR
Watchdog
Timer
WDGR
CPU
A
A/D Converter Data Register
A/D Converter Control Register
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
Reserved (3 Bytes)
Watchdog Register
Reserved (38 Bytes)
Accumulator
xxh
40h
7Fh
0FFh
00h
Read-only
Ro/Wo
R/W
R/W
R/W
0FEh R/W
xxh R/W
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the register.
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Data Registers if any pin of the port is configured
in input mode (refer to Section 8 ”I/O PORTS” on page 37 for more details)
4. Depending on device. See device summary on page 1.
12/105
1
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| PDF Download | [ ST6209C Schematic.PDF ] | |
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