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XE3005 Schematic ( PDF Datasheet ) - ETC
| Teilenummer | XE3005 |
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| Beschreibung | (XE3005 / XE3006) Low-Power Audio CODEC | |
| Hersteller | ETC | |
| Logo |  |
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Gesamt 32 Seiten 
Data Sheet
XE3005/XE3006
VSSD VSSA VSSA VDD VREF
VREG11
VREG16
Microphone
Bias
XE3006
AIN
Amp.
Σ∆
modulator
Decimator
Power supply
management
PWM
DAC
Power
amplifier
SPI
Sandman
Functions
Serial Audio
Interface
Clock
mgt
RESET
VDDPA
AOUTP
AOUTN
VSSPA
MISO SS SCK MOSI SMAD SMDA BCLK SDI SDO FSYNC MCLK
XE3005 / XE3006
Low-Power Audio CODEC
General Description
The XE3005 is an ultra low-power CODEC (Analog
to Digital and Digital to Analog Converter) for voice
and audio applications. It includes microphone
supply, preamplifier, 16-bit ADC, 16-bit DAC, serial
audio interface, power management and clock
management for the ADC and the DAC. The
sampling frequency of the ADC and of the DAC
can be adjusted from 4 kHz to 48 kHz.
The XE3006 also includes the Sandman™
function, which signals whether a relevant voice or
audio signal is present for the ADC or DAC.
Features
• Ultra low-power consumption, below 2 mW
• Low-voltage operation down to 1.8 V
• Sandman™ function to reduce system
power consumption (XE3006)
• Single supply voltage
• Adjustable sampling frequency: 4 – 48 kHz
• Digital format: 16 bit 2s complement
• Requires a minimum number of external
components
• Easy interfacing to various DSPs
• Direct connection to microphone and
speaker
• Various programming options
Applications
• Wireless Headsets
• Bluetooth™ headset
• Hands-free telephony
• Digital hearing instruments
• Consumer and multimedia applications
• All battery-operated portable audio
devices
Quick Reference Data
• supply voltage
• current (@20 kHz sampling)
• sampling frequency
• Typical dynamic range ADC
• Typical dynamic range DAC
1.8 – 3.6 V
0.4 mA
4 – 48 kHz
78 dB
78 dB
Ordering Information
Part Package
Ext. part no.
XE3005 TSSOP 20 pins
XE3006 TSSOP 24 pins
XE3005I033
XE3006I019
Temperature
range
-20 to 70° C
-20 to 70° C
Cool Solutions for Wireless Connectivity
XEMICS SA • e-mail: info@xemics.com • web: www.xemics.com
 
Data Sheet
XE3005/XE3006
2.1.3 DAC Signal Channel
The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling
rate. The outputs of the modulator are 2’s complement words of 6 bit. A pulse-width modulator (PWM) converts
the 6 bit words into 2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are
supplied to the power amplifier. The Power Amplifier is a Class D amplifier, which offers higher efficiency than the
traditional Class AB topologies. It uses a three-state unbalanced PWM. This means that both channels of the PA
(AOUTP and AOUTN) will not switch at the same time, therefore the outputs are not purely differential (see figure
5 and 6)
XE3005/6
From Serial Audio
Interface
Interpolator
&
Modulator
Pulse Width
Modulator
P
N
dac_in(15:0)
@ Fsync
pwm_in(5:0)
@ 8xFsync
bit streams
@ 256xFsync
VDDPA
PN
Power
Amplifier
PN
AOUTP
AOUTN
VSSPA
s
s=1 s=0
Figure 5: DAC block diagram
Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the
time-axis).
pwm_in(5:0) = 1
1
0
1
0
VDDPA
VSSPA
-VDDPA
1/(256 x Fsync)
pwm_in(5:0) = -1 pwm_in(5:0) = 0
1/(256 x Fsync)
1/(8 x Fsync)
pwm_in(5:0) = 2
P
N
OUTP-OUTN
2/(256 x Fsync)
Figure 6: examples PWM in and out (not to scale)
The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be
selected through register J. The complete DAC and PA amplifier chain can be powered-down through register I.
6 D0212-116
6 Page 
Data Sheet
XE3005/XE3006
3 Serial Communications
3.1 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are
listed below:
• BCLK:
• FSYNC:
• SDI:
• SDO:
Bit serial clock, one clock cycle corresponds to one data bit transmitted or received.
Frame Synchronization. This signal indicates the start of a data word. The frequency of
the FSYNC corresponds to the sample frequency of the CODEC.
Serial Data In, data received from external device and sent to DAC.
Serial Data Out, data received from ADC and sent to external device.
The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The
synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK.
The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are
referred to as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be
transmitted and received in 2 channels. Which channel is selected depends on the programmed values in the
registers. The two interface protocols are shown below.
FSYNC
BCLK
SDI
SDO
channel 1, sample n
channel 2, no data
channel 1, sample n+1
n15 n14
n15 n14
msb
n0 -
-
n0 -
lsb
-
- n+115
- n+115
msb
Figure 12: Audio interface timing LFS mode, channel 1
FSYNC
BCLK
SDI
SDO
channel 1, sample n
channel 2, sample n
channel 1, sample n+1
n15 n14
n0 -
-
- n+115
n15 n14
msb
n0 -
lsb
-
- n+115
msb
Figure 13: Audio interface timing in SFS mode, channel 1
SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling
edge of BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling
edge of the BLCK. Each rising edge of the FSYNC indicates the start of a new sample.
12 D0212-116
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