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XC2V40 Schematic ( PDF Datasheet ) - Xilinx
| Teilenummer | XC2V40 |
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| Beschreibung | (XC2Vxxx) Virtex-II Platform FPGAs: Complete Data Sheet | |
| Hersteller | Xilinx | |
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Gesamt 30 Seiten 
0
R Virtex™-II Platform FPGAs:
Complete Data Sheet
DS031 August 1, 2003
0 0 Product Specification
This document includes all four modules of the Virtex-II Platform FPGA data sheet.
Module 1:
Introduction and Overview
DS031-1 (v2.0) August 1, 2003
7 pages
• Summary of Features
• General Description
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
DS031-2 (v3.0) August 1, 2003
40 pages
• Detailed Description
• Digitally Controlled Impedance (DCI)
• Configurable Logic Blocks (CLBs)
• Sum of Products
• 3-State Buffers
• 18-Kb Block SelectRAM™ Resources
• 18-Bit x 18-Bit Multipliers
• Global Clock Multiplexer Buffers
• Digital Clock Manager (DCM)
• Active Interconnect Technology
• Creating a Design
• Configuration
Module 3:
DC and Switching Characteristics
DS031-3 (v3.0) August 1, 2003
38 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
Module 4:
Pinout Information
DS031-4 (v2.0) August 1, 2003
225 pages
• Pin Definitions
• Pinout Tables
- CS144 Chip-Scale BGA Package
- FG256 Fine-Pitch BGA Package
- FG456 Fine-Pitch BGA Package
- FG676 Fine-Pitch BGA Package
- BG575 Standard BGA Package
- BG728 Standard BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- BF957Flip-Chip BGA Package
IMPORTANT NOTE: The Virtex-II Platform FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" pane for easy
navigation in this volume.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS031 August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
 
R Virtex™-II Platform FPGAs: Introduction and Overview
Boundary Scan
Boundary scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II devices that complies with IEEE standards
1149.1 — 1993 and 1532. A system mode and a test mode
are implemented. In system mode, a Virtex-II device per-
forms its intended mission even while executing non-test
boundary-scan instructions. In test mode, boundary-scan
test instructions control the I/O pins for testing purposes.
The Virtex-II Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II devices are configured by loading data into internal
configuration memory, using the following five modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration
information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II configuration memory
can be read back for verification. Along with the configura-
tion data, the contents of all flip-flops/latches, distributed
SelectRAM, and block SelectRAM memory resources can
be read back. This capability is useful for real-time debug-
ging.
The Integrated Logic Analyzer (ILA) core and software pro-
vides a complete solution for accessing and verifying
Virtex-II devices.
Virtex-II Device/Package Combinations
and Maximum I/O
Wire-bond and flip-chip packages are available. Table 4 and
Table 5 show the maximum possible number of user I/Os in
wire-bond and flip-chip packages, respectively. Table 6
shows the number of available user I/Os for all device/pack-
age combinations.
• CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
• FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
• BG denotes standard BGA (1.27 mm pitch).
• BF denotes flip-chip BGA (1.27 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD) and VBATT.
Table 4: Wire-Bond Packages Information
Package
CS144
FG256
Pitch (mm)
0.80 1.00
Size (mm)
12 x 12
17 x 17
I/Os 92 172
FG456
1.00
23 x 23
324
FG676
1.00
27 x 27
484
BG575
1.27
31 x 31
408
BG728
1.27
35 x 35
516
Table 5: Flip-Chip Packages Information
Package
FF896
Pitch (mm)
1.00
Size (mm)
31 x 31
I/Os 624
FF1152
1.00
35 x 35
824
FF1517
1.00
40 x 40
1,108
BF957
1.27
40 x 40
684
DS031-1 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
5
6 Page 
R Virtex™-II Platform FPGAs: Detailed Description
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
(O/T) 1
(O/T) CE
(O/T) CLK1
Shared SR
by all
registers REV
(O/T) CLK2
(O/T) 2
FF
LATCH
D1 Q1
Attribute INIT1
INIT0
SRHIGH
SRLOW
CE
CK1
SR REV
FF1
DDR MUX
FF2
(OQ or TQ)
FF
LATCH
D2 Q2
CE
CK2
SR REV
Attribute INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
Figure 4: Register / Latch Configuration in an IOB Block
DS031_25_110300
Input/Output Individual Options
Each device pad has optional pull-up and pull-down in all
SelectI/O-Ultra configurations. Each device pad has
optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in Figure 5.
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ, which is the specification for VCCO
when operating at 3.3V (from 3.0 to 3.6V only). The clamp
diode is always present, even when power is not.
OBUF
VCCO
Clamp
Diode
Program Current
VCCO
10-60KΩ
Weak
Keeper
Program
Delay
VCCO
10-60KΩ
IBUF
Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards
PAD
VCCAUX = 3.3V
VCCINT = 1.5V
DS031_23_011601
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
4
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