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Teilenummer | MSM66507 |
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Beschreibung | OLMS-66K Series 16-Bit Microcontroller | |
Hersteller | OKI electronic componets | |
Logo | ![]() |
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Gesamt 24 Seiten ![]() E2E1028-27-Y5
¡¡ SemicondSucetormiconductor
MSM66507/66P507
OLMS-66K Series 16-Bit Microcontroller
ThisMveSrMsio6n6:50Ja7n/6. 619P95807
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM66507/66P507 is a high-performance 16-bit microcontroller that employs OKI
original nX-8/500 CPU core.
The MSM66507/66P507 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports,
flexible timers, a pulse-width modulator (PWM), and I/O ports.
FEATURES
• Program memory space
: 64K bytes
Internal ROM
: 48K bytes
• Data memory space
: 64K bytes
Internal RAM
: 1.5K bytes
• High-speed execution
Minimum instruction execution time : 167ns (@24MHz)
• Powerful instruction set
: Instruction set superior in orthogonal matrix
8/16-bit data transfer instructions
8/16-bit arithmetic instructions
Multiplication and division operation instructions
Bit manipulation instructions
Bit logic operation instructions
ROM table reference instructions
• Abundant addressing modes
: Register addressing
Page addressing
Pointing register indirect addressing
Stack addressing
Immediate value addressing
• I/O port
Analog input port
: 1 port ¥ 10 bits
Input-output port
: 7 ports ¥ 8 bits, 1 port ¥ 3 bits
(Each bit can be assigned to input or output.)
• Flexible timers
Free run counters
: 19-bit ¥ 1, 16-bit ¥ 1
19-bit CAP with a divider
:4
16-bit double buffer RTO
:4
16-bit RTO/PWM
:2
16-bit CAP/RTO
:2
• 8-bit general timer
:1
8-bit event counter
:1
• 16-bit PWM
:4
Input clock divider
:2
• Serial ports
UART mode with BRG
:1
Synchronous/UART switchable mode
with BRG
:1
• 10-bit A/D converter
: 10 channels
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![]() ![]() ¡ Semiconductor
MSM66507/66P507
PIN DESCRIPTION (Continued)
Symbol
ALE
PSEN
OE
Type
O
O
I
Description
Timing pulse output pin to latch the lower 8 bits of the address output from port
0 when the CPU accesses the external memory
Strobe pulse output pin to fetch to external program memory
Normally, when P0, P1, and P7.4-P7.7 are in an output state and the OE pin is
"H" level, the ports go to a high impedance state. When OE pin is "L" level,
the ports output "H" or "L" level. However, when P0, P1, and P7.4-P7.7 are in
an input state, these ports are not under the influence of OE pin.
NMI I Nonmaskable interrupt request input pin
RES
RESET input pin
I
Low-active reset input pin
EA
Normally set to "H" level. If set to "L" level, the program memory goes to external
I access mode and accesses external program memory.
VDD I Power supply pin
GND I Ground pin
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6 Page ![]() ![]() ¡ Semiconductor
MSM66507/66P507
SFR (Continued)
Address
[H]
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9I
00CA
00CB
00CC
00CD
00CE
00CFI
00D0I
00D1I
00D2
00D8I
00D9I
00DAI
00DBI
00DCI
00DDI
00DEI
00DFI
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00ECI
00EDI
00EEI
00EFI
Name
TMR4 buffer register
TMR5 buffer register
TMR6 buffer register
TMR7 buffer register
Timer control register
Timer counter 0 lower 3-bit
Timer counter 0
Timer counter 1
Capture control register 0
Capture control register 1
Event control register
TMR mode register
Event dividing counter 0
Event dividing counter 1
Event dividing counter 2
Event dividing counter 3
EVDV0 buffer register
EVDV1 buffer register
EVDV2 buffer register
EVDV3 buffer register
A/DC result register 0
A/DC result register 1
A/DC result register 2
A/DC result register 3
A/DC result register 4
A/DC result register 5
A/DC result register 6
A/DC result register 7
A/DC result register 8
A/DC result register 9
A/DC result register lower 0
A/DC result register lower 1
A/DC result register lower 2
A/D interrupt control register
A/DC control register L
A/DC control register H
Symbol
TMR4BF
TMR5BF
TMR6BF
TMR7BF
TMCON
TM0L
TM0
TM1
CAPCON0
CAPCON1
EVNTCONL
EVNTCONH
TMRMODE
EVDV0
EVDV1
EVDV2
EVDV3
EVDV0BF
EVDV1BF
EVDV2BF
EVDV3BF
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
ADCR8
ADCR9
LADCR0
LADCR1
LADCR2
ADINTCON
ADCONL
ADCONH
R/W
R/W
8/16-bit
Operation
8/16
8
8/16
8
8/16
Reset
00
00
00
00
00
00
00
00
00
1F
00
00
00
00
00
F0
88
88
00
C0
C0
C0
C0
C0
C0
C0
C0
*8/16
R Undefined
8
R/W
F0
80
80
Note: A I mark in the address column shows that there is a bit that does not exist in its register.
* 8/16 means a special word manipulation. (For details, refer to the User's Manual.)
12/24
12 Page | ||
Seiten | Gesamt 24 Seiten | |
PDF Download | [ MSM66507 Schematic.PDF ] |
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