PDF MSM6690 Data sheet ( Hoja de datos )

Número de pieza	MSM6690
Descripción	ROM Interface IC
Fabricantes	OKI electronic componets
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No Preview Available ! ¡¡SemicondSucetormiconductor MSM6690 ROM Interface IC MSM6690 GENERAL DESCRIPTION The MSM6690 can drive three devices of 131,072 x 8-bit EPROM or Mask ROM. The MSM6690 contains a built-in internal address generator circuit and one external clock input that enables contiued serial read operations. The internal address counter is automatically incremented by one each read operation. The external serial address input allows 1,024 words to be addressed in the X-direction, and 1,024 words in the Y-direction. * ROM is selected through CS1, CS2 and CS3 pins. FEATURES • Capable of driving three devices of 1 Mbit EPROM • Capable of driving three devices of 1 Mbit Mask ROM • Supply voltage : Single 5 V • Package options : 42-pin plastic DIP (DIP42-P-600) (Product name: MSM6690RS) 44-pin plastic QFP (QFP44-P-910-2K) (Product name: MSM6690GS-2K) * Available combinations MSM6388/6588 + MSM6389/6587/6586 + MSM6690 + ROM MSM6688/6788/6789A + (MSM6684/6685) + MSM6690 + ROM Note: When driving the MSM6690 with the MSM6388 or the MSM6588, a serial register (MSM6389, MSM6688 or MSM6586) is required. In the case of the MSM6688, MSM6788 and MSM6789A, a playback system can be constructed without a serial register (MSM6684 or MSM6685). 1 page ¡ Semiconductor PIN DESCRIPTIONS Symbol VDD GND SADX Type — — I SADY I SASX SASY TAS I I I RDCK I DOUT O CS1 I CS2 CS3 CE2 CE3 A0 - A16 D0 - D7 TEST TEST01 TEST02 O O I I O MSM6690 Description Power Supply Ground (SERIAL ADDRESS) Starting X address. 1024 words are addressed, and 1024 address data can be input as serial data of 10 bit (AX0 to AX9) via SADX pin. (SERIAL ADDRESS) Starting Y address. 1024 words are addressed, and 1024 address data can be input as serial data of 10 bit (AY0 to AY9) via SADY pin. (SERIAL ADDRESS STROBE) Clock to load X address's serial address data to internal register. (SERIAL ADDRESS STROBE) Clock to load Y address's serial address data to internal register. (TRANSFER ADDRESS STROBE) Serial address data loaded in address register, to internal address counter. X address and Y address data are loaded at fall of TAS pin. (READ CLOCK) Clock to read data in data register. Internal operation starts on falling edge of RDCK, and data in the data register is output via DOUT pin. And internal address counter is automatically incremented by one due to the falling of RDCK. (DATA OUT) In case CS1, CS2 and CS3 are all at "H" level, or RDCK is at "H" level data output pin is always at high impedance state. When "H" level data or "L" level data is read out, output pin is set to "H" level or "L" level and its read data is kept until RDCK turns to "H" level. (CHIP SELECT) Three ROMS selection. CS1 CS2 CS3 CE2 CE3 L —— H H H L—L H HHLHL HHHHH When CS1, CS2 and CS3 are all set to "H" level, all input/output pins become disabled. By use of these pins, three ROM data output pins can be connected in parallel. (CHIP ENABLE) ROM enable. Connect it to ROM's CE. (ADDRESS OUT) ROM address. (DATA IN) ROM data. IC test. Input "L" level data. IC test. Set to open. 5 Page

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