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MSM6636B Schematic ( PDF Datasheet ) - OKI electronic componets

Teilenummer MSM6636B
Beschreibung SAE-J1850 Multiplex Communication Protocol Conformity Transmission Controller for Automotive LAN
Hersteller OKI electronic componets
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Gesamt 13 Seiten
MSM6636B Datasheet, Funktion
E2E1035-27-Y2
¡ Semiconductor¡ Semiconductor
This version:MJSanM. 61699386B
Previous version: Nov. 1996
MSM6636B
SAE-J1850 Multiplex Communication Protocol Conformity Transmission Controller for
Automotive LAN
GENERAL DESCRIPTION
The MSM6636B is a transmission controller for automotive LAN based on data communication
protocol SAE-J1850. This device can realize a data bus topology bus LAN system with a PWM
bit encoding method (41.6 kbps). In addition to a protocol control circuit, MSM6636B has an
enclosed quartz oscillation circuit, host CPU interface (parallel interface), a transmit/receive
buffer, and a bus receiver circuit that decreases the burden on the host CPU.
FEATURES
• Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued
August 12, 1991)
• Non-destructive collision and priority control using CSMA/CD
• Internal transmit buffer (1 frame) and receive buffer (2 frames)
• Modulating/demodulating: PWM (Pulse Width Modulation)
• Transmission speed: 41.6 kbps
• Multi-address setting with physical addressing: 1 type / functional addressing: 15 types
• Address filter function by multi-addressing (broadcasting possible)
• Automatic retransmission function by arbitration loss and non ACK
• Three types of in-frame response support:
q Single-byte response from a single node
w Multi-byte response from a single node (with CRC code)
e Single-byte response from multiple nodes (ID response as ACK)
• Error detection by cyclic redundancy check (CRC)
• Various communication error detections
• Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function
• Host CPU interface is accessed in parallel
• Sleep function
Low current consumption mode by oscillation stop (IDS Max < 50µA)
SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus
• Package: 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6636BGS-K)
1/13






MSM6636B Datasheet, Funktion
¡ Semiconductor
MSM6636B
AC Chacteristics
• PWM bit timing
Parameter
Bit Length
"1" Dominant Width
"0" Dominant Width
"SOF" Dominant Width
"SOF, BRK" Length
"BRK" Dominant Width
"EOD" + Bit Length
"EOF" + Bit Length
"EOF + IFS" " + Bit Length
"0" Passive Width
Symbol
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
DVDD=AVDD=5V±10%, Ta=–40 to +85°C, In setting 41.6 kbps
Transmit
min typ max
Receive
min max
Unit
23.64 24.00 24.36 21.00 28.00 ms
6.90 7.00 7.11 5.00 12.00 ms
14.87 15.00 15.23 13.00 20.00 ms
30.54 31.00 31.47 29.00 36.00 ms
47.28 48.00 48.72 45.00 52.00 ms
38.42 39.00 39.59 37.00 44.00 ms
47.28 48.00 48.72 43.00 51.00 ms
70.92 72.00 — 69.00 76.00 ms
94.56 96.00 — 86.00 — ms
8.86 9.00 9.14 4.00 15.00 ms
Note: The sending timing in the above table does not include the delay of the bus drivers.
Dominant
"1"
Passive
TP2
Dominant
"0 "
Passive
Dominant
" SOF "
Passive
Dominant
" EOD "
Passive
Dominant
" EOF "
" IFS "
Passive
Dominant
" BRK "
Passive
TP3
TP1
TP10
TP4
TP5
LAST BIT
TP7
EOD
LAST BIT
EOF
TP8
TP9
TP6
TP5
IFS
6/13

6 Page









MSM6636B pdf, datenblatt
¡ Semiconductor
MSM6636B
APPLICATION CIRCUIT
Host CPU and J1850 Line Bus Connection Example
Host CPU
AD0-7
ALE
RD
WR
PXX
INT
CLKOUT
RES
MSM6636B
AD0-7
ALE
RD
WR
CS
INT
DVDD AVDD
BO (+)
BI (+)
C
*1 BI (–)
OSC0
BO (–)
OPEN OSC1 RES DGND AGND
RB
RR
RR
RB
Unit A
RS
ZD
ZD
RS
Unit B
RP
. RD
.
.
Bus + Bus –
An optimum system can be constructed by selecting an optimum host CPU and combining it
with the MSM6636B.
*1 Insert a capacitor between the power supply and GND to prevent supply noise.
It is recommended to connect a small-capacitance bypass capacitor and a large-capacitance
filter capacitor serially. The typical capacitors are as follows:
0.01 to 0.22 mF : Ceramic capacitor
10 to 100 mF : Tantalum capacitor
12/13

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