MSM6648 Schematic ( PDF Datasheet ) - OKI electronic componets

Teilenummer	MSM6648
Beschreibung	100-DOT COMMON DRIVER
Hersteller	OKI electronic componets
Logo
Gesamt 9 Seiten E2B0029-27-Y2 ¡¡SemicondSucetormiconductor MSM6648 100-DOT COMMON DRIVER This version: NMovS.M19696748 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM6648 is a dot matrix LCD common driver. Fabricated in CMOS technology, the device consists of two 50-bit bidirectional shift registers, two 50-bit level shifters, and two 50-bit 4-level drivers. The MSM6648 is equipped with 100 LCD output pins. By connecting more than two MSM6648s in cascade, this LSI is applicable to a wide LCD panel. FEATURES • Logic supply voltage : 2.7 to 5.5 V • LCD drive voltage : 18 to 28 V • Applicable LCD duty : 1/64 to 1/240 • Suitable for bath panel sizes of 400 (200 ¥ 2) and 480 (240 ¥ 2) in common numbers by the use of intermediate data input and 10-bit bypass function. • Structure: Tape Carrier Package (TCP) mounting with 35 mm wide film (Product name : MSM6648AV-Z-01) Sn-plated 1/9 ¡ Semiconductor MSM6648 FUNCTIONAL DESCRIPTION Pin Functional Description • IO, IO50, IO51, IO100 These are I/O pins for the two 50-bit bidirectional shift registers. • SHL This is an input pin to select the shift direction of the two 50-bit bidirectional shift registers. Set this pin to "H" or "L" level during power-on. • MODE1, MODE2 These are input pins to select whether the two 50-bit shift registers are used as a two 50-bit application or a 40-bit and 50-bit application. Functions of the SHL, MODE1 and MODE2 pins are shown below. Scan Data Scan SHL MODE1 MODE2 direction input pin output pin Function L— HL L— O1 Æ O50 IO1 L O51 Æ O100 IO51 O50 Æ O1 IO50 — O100 Æ O51 IO100 O11 Æ O50 IO1 H O51 Æ O100 IO51 IO50 IO100 IO1 IO51 IO50 IO100 The scan data input into the IO1, and IO51 pins are shifted at the falling edge of CP and are output from the IO50 and IO100 pins after the lapse of 50 clock pulses. The scan data input into the IO100 and IO50 pins are shifted at the falling edge of CP and are output from the IO51 and IO1 pins after 50 clock pulses. This condition means a mode of bypassing between the O1 and O10 pins. The scan data input into the IO1 pin is stored in the O11 pin and is output from the IO50 pin after 40 clock pulses. The operation in the O51 to O100 pins is the same as that in setting SHL to "L" and MODE2 to "L". HH O50 Æ O1 IO50 — O90 Æ O51 IO100 This condition means a mode of bypassing IO1 between the O91 and O100 pins. The scan data input into the IO100 pin is stored in O90 and is output from the IO51 pin after 40 clock pulses. IO51 The operation in the O1 to O50 pins is the same as that in setting SHL to "H" and MODE1 to "L". 6/9 6 Page
Seiten	Gesamt 9 Seiten
PDF Download	[ MSM6648 Schematic.PDF ]

Link teilen

Besondere Datenblatt

Teilenummer	Beschreibung	Hersteller
MSM6641	Built-in Remote Control Transmission Circuit 4-Bit Microcontroller	OKI electronic componets
MSM6641E-xx	Built-in Remote Control Transmission Circuit 4-Bit Microcontroller	OKI electronic componets
MSM6648	100-DOT COMMON DRIVER	OKI electronic componets

Teilenummer	Beschreibung	Hersteller
CD40175BC	Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.	Fairchild Semiconductor
KTD1146	EPITAXIAL PLANAR NPN TRANSISTOR.	KEC