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UPD485506 Schematic ( PDF Datasheet ) - NEC
| Teilenummer | UPD485506 |
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| Beschreibung | LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT | |
| Hersteller | NEC | |
| Logo |  |
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Gesamt 24 Seiten 
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
Description
The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either
5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power
consumption.
The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus
the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals.
There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions
operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
• 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)
• Asynchronous read/write operations available
• Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)
15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)
• Power supply voltage VCC = 5.0 V ±0.5 V
• Suitable for sampling two lines of A3 size paper (16 dots/mm)
• All input/output TTL compatible
• 3-state output
• Full static operation; data hold time = infinity
Ordering Information
Part Number
µPD485506G5-25-7JF
µPD485506G5-35-7JF
R/W Cycle Time
25 ns
35 ns
Package
44-pin plastic TSOP (II) (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. M10060EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1994
 
µPD485506
2.2 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
line (5,048 bits or 10,096 bits) delay and write data can be processed with the same clock. Refer to Write Cycle
Timing Chart.
When WE is disabled (“H” level) in a write cycle, the write operatoin is not performed during the cycle which
the WCK rising edge is in the WE = “H” level (tWEW). The WCK does not increment the write address pointer
at this time.
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
incrementing again.
2.3 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input.
When the OE input is also enabled (“L” level) at that time, data is output after tAC. Refer to Read Cycle Timing
Chart.
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
the RCK rising edge is in the RE = “H” level (tREW). The RCK does not increment the read address pointer at
this time.
2.4 Write Reset Cycle/Read Reset Cycle
After power up, the µPD485506 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE, WE or
OE.
6 Data Sheet M10060EJ7V0DS00
6 Page 
Write Reset Cycle Timing Chart (WE = Active)
Cycle n
Reset Cycle
WCK (Input)
RSTW (Input)
tRN1
tRS
tRSTW Note
Cycle 0
tRH tRN2
µPD485506
Cycle 1
WE (Input) “L” Level
DIN (Input) (n–1)
tDS tDH
(n)
tDS tDH
(0)
(1)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle Timing Chart (WE = Inactive)
Cycle n
Disable Cycle
Reset Cycle
Cycle 0
WCK (Input)
RSTW (Input)
WE (Input)
tRN1
tWEN1
DIN (Input) (n–1)
tRS tRSTW Note
tWES
tDS tDH
(n)
tWEW
tRH tRN2
tWEH
tWEN2
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
tDS
(0)
12 Data Sheet M10060EJ7V0DS00
12 Page | ||
| Seiten | Gesamt 24 Seiten | |
| PDF Download | [ UPD485506 Schematic.PDF ] | |
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