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UPD485505 Schematic ( PDF Datasheet ) - NEC
| Teilenummer | UPD485505 |
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| Beschreibung | LINE BUFFER 5K-WORD BY 8-BIT | |
| Hersteller | NEC | |
| Logo |  |
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Gesamt 20 Seiten 
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD485505
LINE BUFFER
5K-WORD BY 8-BIT
Description
The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry
provides high speed access and low power consumption.
The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus
the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied
to the version P and L. These versions operate with different specifications. Each version is identified with its lot
number (refer to 7. Example of Stamping).
Features
• 5,048 words by 8 bits
• Asynchronous read/write operations available
• Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)
15 to 5,048 bits (Cycle time: 35 ns)
• Power supply voltage VCC = 5.0 V ± 0.5 V
• Suitable for sampling one line of A3 size paper (16 dots/mm)
• All input/output TTL compatible
• 3-state output
• Full static operation; data hold time = infinity
Ordering Information
Part Number
µPD485505G-25
µPD485505G-35
R/W Cycle Time
25 ns
35 ns
Package
24-pin plastic SOP
(11.43 mm (450))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. M10059EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1994,1996
 
µPD485505
Operation-related Restriction
Following restriction exists to read data written in a write cycle.
Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1).
If tWAR is not satisfied, the output data may undefined.
Figure 2.1 Delay Bits Restriction Timing Chart
WCK
0123
1/2 write cycle
tWAR
RCK
High
DIN impedance
0
DOUT
1 23
High impedance
012
tAC
0 1 23
Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR
signals.
6 Data Sheet M10059EJ7V0DS00
6 Page 
Read Reset Cycle Timing Chart (RE = Active)
Cycle n
Reset Cycle
Cycle 0
Cycle 1
µPD485505
RCK (Input)
RSTR (Input)
tRN1
tRS tRSTR Note
tRH tRN2
RE (Input)
“L” Level
tAC
DOUT (Output) (n–1)
tAC
(n)
tOH
tAC
(0)
tAC
(0)
tOH
(1)
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
tOH
Read Reset Cycle Timing Chart (RE = Inactive)
Cycle n
Disable Cycle
Cycle 0
Reset Cycle
RCK (Input)
RSTR (Input)
tRN1 tRS tRSTR Note
tREN1
tRES
tRH tRN2
tREH
tREN2
RE (Input)
DOUT (Output) (n–1)
tAC
tREW
tHZ
(n)
tOH
High impedance
tAC
tLZ
(0)
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
tOH
12 Data Sheet M10059EJ7V0DS00
12 Page | ||
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| PDF Download | [ UPD485505 Schematic.PDF ] | |
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