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PDF LPC47B34X Data sheet ( Hoja de datos )
| Número de pieza | LPC47B34X | |
| Descripción | 128 PIN ENHANCED SUPER I/O | |
| Fabricantes | Standard Microsystems | |
| Logotipo |  |
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LPC47B34x
128 Pin Enhanced Super I/O with LPC Interface
for Consumer Applications
FEATURES
• 3.3 Volt Operation (5V Tolerant)
• LPC Interface
• Floppy Disk Controller (Supports 2 FDCs)
• Multi-Mode Parallel Port
• Two Full UARTs
• 8042 Keyboard Controller (Internal Latch on
IRQ1 and IRQ12)
• Programmable Wakeup Event Interface
(nIO_PME Pin)
• SMI Pin
• GPIOs (62)
• ISA IRQ to Serial IRQ Conversion (11 Pins)
• WDT
• Security Register
• ACPI Support Register for Monitoring
System Sleep State and SMI Generation
• Intrusion Detection
• LED Control
• Low Battery Warning
• Battery Backup of Certain Wakeup Events
• XNOR Chain
• PC99 and ACPI 1.0 Compliant
• ISA Plug-and-Play Compatible Register Set
• Intelligent Auto Power Management
• 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk
Controller
- Software and Register Compatible with
SMSC's Proprietary 82077AA
Compatible Core
- Configurable Open Drain/Push-Pull
Output Drivers
- Supports Vertical Recording Format
- 16-Byte Data FIFO
- 100% IBM® Compatibility
- Detects All Overrun and Underrun
Conditions
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power
Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- 480 Address, up to 15 IRQ and 3 DMA
Options
• Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation
Modes
• Keyboard Controller
- 8042 Software Compatible
- 8-Bit Microcomputer
- 2k Bytes of Program ROM
- 256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 8-Bit Counter Timer
- Port 92 Support
1 page  
GPIO Registers Block Summary .................................................................................................156
Registers Powered by VBAT........................................................................................................157
Runtime Registers Block Description ...........................................................................................157
GPIO Registers Block Description ...............................................................................................194
CONFIGURATION .........................................................................................................................200
OPERATIONAL DESCRIPTION .....................................................................................................222
Maximum Guaranteed Ratings ....................................................................................................222
DC Electrical Characteristics .......................................................................................................222
TIMING DIAGRAMS ......................................................................................................................226
ECP Parallel Port Timing.............................................................................................................237
PACKAGE OUTLINE .....................................................................................................................245
APPENDIX - TEST MODES ...........................................................................................................246
Board Test Mode.........................................................................................................................246
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
5
5 Page 
PIN #
NAME
FUNCTION
BUFFER
TYPE
BUFFER TYPE
PER FUNCTION
(NOTE 6)
126 nRTS2 /GP55
Request to Send 2 /GPIO
IO8 O8 /(I/O8/OD8)
127 nCTS2 /GP56
Clear to Send 2 /GPIO
IO8 I /(I/O8/OD8)
128 nDTR2 /GP57
Data Terminal Ready 2 /GPIO
IO8 O8 /(I/O8/OD8)
POWER PINS
19,80, VCC
+3.3 Volt Supply Voltage
121
15 VTR
Standby Supply Voltage
46 VBAT
Battery Voltage
6,32, VSS
Ground
57,87,
99
52 AVSS
Analog Ground
CLOCK PINS
16 CLKI32
32.768kHz Standby Clock Input
IS
IS
20 CLOCKI
14.318MHz Clock Input
IS IS
Note 1: The nLPCPD pin may be pulled high. The LPC interface will function properly if the
nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin
Count Interface Specification”.
Note 2: These pins default to a reserved function and must be programmed to their GPIO function
immediately following power-up.
Note 3: The nKBDRST and A20M functions must default to high on VCC POR and Hard Reset.
Note 4: This pin requires an external pulldown resistor to put the base I/O address for configuration at
0x02E. An external pullup resistor is required to move the base I/O address for configuration
to 0x04E.
Note 5: The TXD2 pin will power up as an output and low following a VCC POR and Hard Reset due
to its IR functionality.
Note 6: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in
parenthesis represent multiple buffer types for a single pin function.
Note 7: If the 32kHz clock is not used, the CLKI32 pin must be grounded. Bit 0 of the CLKI32
configuration register located at 0xF0 in Logical Device A must be set to ‘1’.
Note 8: The GP35/IRTX2 pin powers up as an output and high on VTR POR, VCC POR and Hard
Reset. This pin and GP34/IRRX2 pin are not recommended to be used for IR functionality.
Buffer Type Descriptions
Engineering Note: The buffer type values are specified at VCC=3.3V
IO12
Input/Output, 12mA sink, 6mA source.
IS/O12
Input with Schmitt Trigger/Output, 12mA sink, 6mA source.
O12 Output, 12mA sink, 6mA source.
OD12
Open Drain Output, 12mA sink.
O6 Output, 6mA sink, 3mA source.
IO8 Input/Output, 8mA sink, 4mA source.
IS/O8
Input with Schmitt Trigger/Output, 8mA sink, 4mA source.
O8 Output, 8mA sink, 4mA source.
OD8
Open Drain Output, 8mA sink.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC47B34X.PDF ] | |
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