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ST92195B Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST92195B
Beschreibung 32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 22 Seiten
ST92195B Datasheet, Funktion
ST92195B
32-64K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING
s Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
s 0°C to +70°C operating temperature range
s Up to 24 MHz. operation @ 5V±10%
s Min. instruction cycle time: 165ns at 24 MHz.
s 32, 48, 56 or 64 Kbytes ROM
s 256 bytes RAM of Register file (accumulators or
index registers)
s 256 bytes of on-chip static RAM
s 2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
s 28 fully programmable I/O pins
s Serial Peripheral Interface
s Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
s Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, defin-
able by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes
s Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
s VPS and Wide Screen Signalling slicer (on
some devices)
s Integrated Sync Extractor and Sync Controller
s 14-bit Voltage Synthesis for tuning reference
voltage
s Up to 6 external interrupts plus one Non-
Maskable Interrupt
s 8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
s 16-bit watchdog timer with 8-bit prescaler
s One 16-bit standard timer with 8-bit prescaler
s 4-channel A/D converter; 5-bit guaranteed
PSDIP56
TQFP64
See end of document for ordering information
s Rich instruction set and 14 addressing modes
s Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
s Pin-compatible EPROM and OTP devices
available
Device Summary
Device
ST92195B1
ST92195B2
ST92195B3
ST92195B4
ST92195B5
ST92195B6
ST92195B7
ST92T195B7
ST92E195B7
Program
Memory
32K ROM
32K ROM
32K ROM
48K ROM
48K ROM
56K ROM
64K ROM
64K OTP
64K EPROM
TDS
RAM
2K
6K
6K
6K
8K
8K
8K
8K
8K
VPS/
WSS
Package
Yes
No
Yes
Yes PSDIP56/
Yes TQFP64
Yes
Yes
Yes
Yes
CSDIP56
/CQFP64
Rev. 2.5
January 2000
1/22
1






ST92195B Datasheet, Funktion
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
RESET Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
FB Fast Blanking. Video analog DAC output.
VDD Main power supply voltage (5V±10%, digital)
WSCF, WSCR Analog pins for the VPS/WSS slic-
er . These pins must be tied to ground or not con-
nected.
VPP: On EPROM/OTP devices, the WSCR pin is
replaced by VPP which is the programming voltage
pin. VPP should be tied to GND in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
Figure 3. 56-Pin Package Pin-Out
I NT7/P2. 0
RES ET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0 .2
P0.1
P0.0
CSO/RE SET0/P3.7
P3.6
P3.5
P3.4
B
G
R
FB
SDI/SDO/ P5.1
SCK/INT2/P5. 0
VDD
JTDO
WSC F
VPP/WSCR
AVDD3
TEST 0
MCFM
JTCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSYNC Vertical Sync. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog VDD of PLL. This pin must be tied
to VDD externally.
GND Digital circuit ground.
AGND Analog circuit ground (must be tied exter-
nally to digital GND).
CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
AVDD1, AVDD2 Analog power supplies (must be
tied externally to AVDD3).
TXCF Analog pin for the Teletext slicer line PLL.
CVBSO, JTDO, JTCK Test pins: leave floating.
TEST0 Test pins: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
56 P2.1/INT5/AIN1
55 P2.2/INT0/AIN2
54 P2.3/INT6/VS01
53 P2.4/NMI
52 P2.5/AIN3/INT4/VS02
51 OSCIN
50 OSCOUT
49 P4.7/PWM7/EX TRG/ST OUT
48 P4.6/PWM6
47 P4.5/PWM5
46 P4.4/PWM4
45 P4.3/PWM3/TSLU/HT
44 P4.2/PWM2
43 P4.1/PWM1
42 P4.0/PWM0
41 VSYNC
40 HSYNC/CSYNC
39 AVDD1
38 PXFM
37 JTRSTO
36 GND
35 AGND
34 CVBS1
33 CVBS2
32 JTMS
31 AVDD2
30 CVBSO
29 TXCF
6/22

6 Page









ST92195B pdf, datenblatt
ST92195B - GENERAL DESCRIPTION
1.3 MEMORY MAP
Internal ROM
The ROM memory is mapped in a single continu-
ous area starting at address 0000h in MMU seg-
ment 00h.
Device
ST92195B1/B2/B3
ST92195B4/B5
ST92195B6
ST92195B7
Size
32K
48K
56K
64K
Start
Address
0000h
0000h
0000h
0000h
End
Address
7FFFh
BFFFh
DFFFh
FFFFh
Internal RAM, 256 bytes
The internal RAM is mapped in MMU segment
20h; from address FF00h to FFFFh.
Internal TDSRAM
The Internal TDSRAM is mapped starting at ad-
dress 8000h in MMU segment 22h. It is a fully stat-
ic memory.
Device
ST92195B1
ST92195B2/B3/B4
ST92195B5/B6/B7
Size
2K
6K
8K
Start
Address
8000h
8000h
8000h
End
Address
87FFh
97FFh
9FFFh
Figure 6. ST92195B Memory Map
max. 8 Kbytes
TDS RAM
229FFFh
228000h
SEGMENT 22h
64 Kbytes
Reserved
Reserved
Reserved
22FFFFh
2 2C000h
2 2BFFFh
2 28000h
2 27FFFh
2 24000h
2 23FFFh
220000h
21FFFFh
PAGE 91 - 16 Kbytes
PAGE 90 - 16 Kbytes
PAGE 89 - 16 Kbytes
PAGE 88 - 16 Kbytes
SEGMENT 21h
64 Kbytes
Reserved
Internal
RA M
256 bytes
20FFFFh
20FF 00h SEGMENT 20h
64 Kbytes
SEGMENT 0
64 Kbytes
Reserved
Reserved
Reserved
Internal ROM
max. 64 Kbytes
210000h
20FFFFh
2 0C000h
2 0BFFFh
2 08000h
2 07FFFh
2 04000h
2 03FFFh
2 00000h
00FFFFh
00C000h
00BFFFh
008000h
007FFFh
004000h
003FFFh
000000h
PAGE 83 - 16 Kbytes
PAGE 82 - 16 Kbytes
PAGE 81 - 16 Kbytes
PAGE 80 - 16 Kbytes
PAGE 3 - 16 Kbytes
PAGE 2 - 16 Kbytes
PAGE 1 - 16 Kbytes
PAGE 0 - 16 Kbytes
12/22

12 Page





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