|
|
PDF AD5255 Data sheet ( Hoja de datos )
| Número de pieza | AD5255 | |
| Descripción | 3-Channel Digital Potentiometer with Nonvolatile Memory | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD5255 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
3-Channel Digital Potentiometer with
Nonvolatile Memory
AD5255
FEATURES
3 channels:
Dual 512-position
Single 128-position
25 kΩ or 250 kΩ full-scale resistance
Low temperature coefficient:
Potentiometer divider 15 ppm/°C
Rheostat mode 35 ppm/°C
Nonvolatile memory retains wiper settings
Permanent memory write protection
Linear increment/decrement
±6 dB increment/decrement
I2C-compatible serial interface
2.7 V to 5.5 V single-supply operation
±2.25 V to ±2.75 V dual-supply operation
Power-on reset time
256 bytes general-purpose user EEPROM
11 bytes RDAC user EEPROM
GBIC and SFP compliant EEPROM
100-year typical data retention at TA = 55°C
APPLICATIONS
Mechanical potentiometer replacement
RGB LED backlight control
White LED brightness adjustment
Programmable gain and offset control
Programmable filters
GENERAL DESCRIPTION
The AD5255 provides dual 512-position and a single
128-position digitally controlled variable resistors1 (VR) in a
TSSOP package. This device performs the same electronic
adjustment function as a potentiometer, trimmer, or variable
resistor. Each VR offers a completely programmable value of
resistance between the A terminal and the wiper or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
25 kΩ or 250 kΩ has a 1% channel-to-channel matching
tolerance and a nominal temperature coefficient of 35 ppm/°C.
Wiper position programming, EEPROM2 reading, and EEPROM
writing is conducted via the standard 2-wire I2C interface. Pre-
vious/default wiper position settings can be stored in memory,
and refreshed upon system power-up.
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
GND
SCL
SDA
A0_RDAC
A1_RDAC
A0_E
A1_E
RS
WP
I2C
SERIAL
INTERFACE
POWER-ON
RESET
256 BYTES
USER
EEPROM
32 BYTES
RDAC
EEPROM
DATA
CONTROL
COMMAND
DECODE
LOGIC
ADDRESS
DECODE
LOGIC
DECODE
LOGIC
RDAC0
9 BIT
RDAC1
9 BIT
RDAC2
7 BIT
A0
W0
B0
A1
W1
B1
A2
W2
B2
Figure 1.
Additional features of the AD5255 include preprogrammed
linear and logarithmic increment/decrement wiper changing.
The actual resistor tolerances are stored in EEPROM so that the
actual end-to-end resistance is known, which is valuable for
calibration in precision applications.
The AD5255 is available in a 24-lead TSSOP package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of −40°C to +85°C.
1 The terms programmable resistor, variable resistor, RDAC, and digital
potentiometer are used interchangeably.
2 The terms nonvolatile memory, EEMEM, and EEPROM are used
interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD5255
ELECTRICAL CHARACTERISTICS
Single Supply: VDD = 3 V to 5.5 V and −40°C < TA< +85°C, unless otherwise noted.
Dual Supply: VDD = +2.25 V or +2.75 V , VSS = −2.25 V or −2.75 V and −40°C < TA < + 85°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC CHARACTERISTICS5, 7
Symbol
Conditions
Min Typ1 Max Unit
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Spectral Density
Digital Crosstalk
Analog Crosstalk
BW
THDW
tS
eN_WB
CT
CAT
VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
VW = 0.50% error band,
code 0x000 to 0x100, RAB = 25 kΩ/250 kΩ
RAB = 25 kΩ/250 kΩ, TA = 25°C
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A0 and measure output
at W1, f = 1 kHz
125/12
0.05
4/36
14/45
−80
−72
kHz
%
µs
nV√Hz
dB
dB
INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes8, 9)
SCL Clock Frequency
tBUF Bus Free Time between Stop and
Start
tHD;STA Hold Time (Repeated Start)
fSCL
t1
t2
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tR Rise Time of Both SDA and SCL
Signals
tF Fall Time of Both SDA and SCL
Signals
tSU;STO Setup Time for Stop Condition
EEMEM Data Storing Time
EEMEM Data Restoring Time at
Power-On
EEMEM Data Restoring Time on
Restore
Command or Reset Operation
t3
t4
t5
t6
t7
t8
t9
t10
tEEMEM_STORE
tEEMEM_RESTORE1
tEEMEM_RESTORE2
After this period the first clock pulse is
generated
1.3
600
1.3
0.6
600
100
600
26
360
360
400 kHz
µs
ns
µs
50 µs
ns
900 ns
ns
300 ns
300 ns
ns
ms
µs
µs
EEMEM Data Rewritable Time
FLASH/EE MEMORY RELIABILITY
Endurance10
Data Retention11
tEEMEM_REWRITE
55°C
540
100
100
µs
kcycles
years
1 Typical represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7 All dynamic characteristics use VDD = 5 V.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 See the timing diagram for location of measured values.
10 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.
11 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.
Rev. 0 | Page 5 of 20
5 Page 
EEPROM INTERFACE
S1 0 1 0 0 AA0A
10
EE
EEPROM SLAVE ADDRESS
0 WRITE
S1 0 1 0 0 AA0A
10
EE
EEPROM SLAVE ADDRESS
1 READ
AD5255
MEMORY ADDRESS
A MEMORY DATA A
MEMORY DATA A/A P
Figure 19. EEPROM Write
MEMORY DATA
A
(N BYTES + ACKNOWLEDGE)
MEMORY DATA
AP
(N BYTES + ACKNOWLEDGE)
Figure 20. EEPROM Current Read
S SLAVE ADDRESS
W A MEMORY ADDRESS
A S SLAVE ADDRESS
R A MEMORY DATA
A/A P
0 WRITE
REPEATED START
Figure 21. EEPROM Random Read
1 READ
(N BYTES + ACKNOWLEDGE)
The 256 bytes of EEPROM memory provided in the AD5255
are organized into 16 pages of 16 bytes each. The word size of
each memory location is one byte wide.
The I2C slave address of the EEPROM is 10100(A1E)(A0E),
where A1E and A0E are external pin-programmable address
bits. The 2-pin programmable address bits allow a total of four
AD5255 devices to be controlled by a single I2C master bus,
each having its own EEPROM.
An internal 8-bit address counter for the EEPROM is
automatically incremented following each read or write
operation. For read operations, the address counter is
incremented after each byte is read, and the counter rolls over
from Address 255 to 0.
For write operations, the address counter is incremented after
each byte is written. The counter rolls over from the highest
address of the current page to the lowest address of the current
page. For example, writing two bytes beginning at Address 31
causes the counter to roll back to Address 16 after the first byte
is written; then the address increments to 17 after the second
byte is written.
EEPROM Write
Each write operation issued to the EEPROM programs between
1 byte and 16 bytes (1 page) of memory. Figure 19 shows the
EEPROM write interface. The number of bytes of data, N, that
the user wants to send to the EEPROM is unrestricted. If more
than 16 bytes of data are sent in a single write operation, the
address counter rolls back to the beginning address, and the
previously sent data is overwritten.
EEPROM Write-Acknowledge Polling
After each write operation, an internal EEPROM write cycle
begins. During the EEPROM internal write cycle, the I2C
interface of the device is disabled. It is necessary to determine if
the internal write cycle is complete and whether the I2C
interface is enabled. To do so, execute I2C interface polling by
sending a start condition followed by the EEPROM slave
address plus the desired R/W bit. If the AD5255 I2C interface
responds with an ACK, the write cycle is complete and the
interface is ready to proceed with further operations. Otherwise,
the I2C interface must be polled again to determine whether the
write cycle has been completed.
EEPROM Read
The AD5255 EEPROM provides two different read operations,
shown in Figure 20 and Figure 21. The number of bytes, N, read
from the EEPROM in a single operation is unrestricted. If more
than 256 bytes are read, the address counter rolls back to the
start address, and data previously read is read again.
Figure 20 shows the EEPROM current read operation. This
operation does not allow an address location to be specified,
and reads data beginning at the current address location stored
in the internal address counter.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5255.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD5251 | (AD5251 / AD5252) Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers | Analog Devices |
| AD5252 | (AD5251 / AD5252) Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers | Analog Devices |
| AD5253 | Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers | Analog Devices |
| AD5254 | Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |