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AD5251 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5251
Beschreibung (AD5251 / AD5252) Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD5251 Datasheet, Funktion
Dual 64-and 256-Position I2C Nonvolatile
Memory Digital Potentiometers
AD5251/AD5252
FEATURES
AD5251: Dual 64-position resolution
AD5252: Dual 256-position resolution
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Nonvolatile memory1 stores wiper setting w/write protection
Power-on refreshed with EEMEM settings in 300 µs typ
EEMEM rewrite time = 540 µs typ
Resistance tolerance stored in nonvolatile memory
12 extra bytes in EEMEM for user-defined information
I2C compatible serial interface
Direct read/write access of RDAC2 and EEMEM registers
Predefined linear increment/decrement commands
Predefined ±6 dB step change commands
Synchronous or aysynchronous dual channel update
Wiper setting read back
4 MHz bandwidth—1 kΩ version
Single supply 2.7 V to 5.5 V
Dual supply ±2.25 V to ±2.75 V
2 slave address decoding bits allow operation of 4 devices
100-year typical data retention TA = 55°C
Operating temperature –40°C to +85°C
APPLICATIONS
Mechanical potentiometer replacement
General purpose DAC replacement
LCD panel VCOM adjustment
GENERAL DESCRIPTION
The AD5251/AD5252 are dual-channel, I2C, nonvolatile mem-
ory, digitally controlled potentiometers with 64/256 positions,
respectively. These devices perform the same electronic adjust-
ment functions as mechanical potentiometers, trimmers, and
variable resistors. The parts’ versatile programmability allows
multiple modes of operation, including read/write access in the
RDAC and EEMEM registers, increment/decrement of
resistance, resistance changes in ±6 dB scales, wiper setting
readback, and extra EEMEM for storing user-defined infor-
mation such as memory data for other components, look-up
table, or system identification information.
The AD5251/AD5252 allow the host I2C controllers to write
any of the 64- or 256-step wiper settings in the RDAC registers
and store them in the EEMEM. Once the settings are stored,
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
White LED brightness adjustment
RF base station power amp bias control
Programmable gain and offset control
Programmable voltage-to-current conversion
Programmable power supply
Sensor calibrations
FUNDAMENTAL BLOCK DIAGRAM
VDD
VSS
DGND
WP
SCL
SDA
AD0
AD1
I2C
SERIAL
INTERFACE
POWER-
ON RESET
RDAC EEMEM
EEMEM
POWER-ON
REFRESH
RAB
TOL
RDAC1
REGIS-
TER
RDAC1
DATA
CONTROL
RDAC3
REGIS-
TER
RDAC3
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL LOGIC
AD5251/
AD5252
A1
W1
B1
A3
W3
B3
Figure 1.
1The terms nonvolatile memory and EEMEM are used interchangeably.
2The terms digital potentiometer and RDAC are used interchangeably.
they are restored automatically to the RDAC registers at system
power-on; the settings can also be restored dynamically.
The AD5251/AD5252 provide additional increment,
decrement, +6 dB step change, and –6 dB step change in
synchronous or asynchronous channel update modes. The
increment and decrement functions allow stepwise linear
adjustments, while ±6 dB step changes are equivalent to
doubling or halving the RDAC wiper setting. These functions
are useful for steep-slope nonlinear adjustments such as white
LED brightness and audio volume control. The parts have a
patented resistance tolerance storing function which enable the
user to access the EEMEM and obtain the absolute end-to-end
resistance values of the RDACs for precision applications.
The AD5251/AD5252 are available in TSSOP-14 packages in
1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options and all parts can
operate over the –40°C to +85°C extended industrial
temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD5251 Datasheet, Funktion
AD5251/AD5252
Parameter
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Symbol
VDD/VSS
IDD
ISS
EEMEM Data Storing Mode
Current
EEMEM Data Restoring Mode
Current6
Power Dissipation7
Power Supply Sensitivity
IDD_STORE
IDD_RESTORE
PDISS
PSS
DYNAMIC CHARACTERISTICS5, 8
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Digital Crosstalk
BW
THDW
tS
eN_WB
CT
Analog Coupling
CAT
Conditions
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = +2.5 V, VSS
= -2.5 V
VIH = VDD or VIL = GND, TA = 0°C to 85°C
VIH = VDD or VIL = GND, TA = 0°C to 85°C
VIH = VDD = 5 V or VIL = GND
∆VDD = 5 V ±10%
∆VDD = 3 V ±10%
Min
±2.25
Typ1
5
−5
35
2.5
−0.005 +0.002
−0.01 +0.002
Max
±2.75
15
−15
Unit
V
µA
µA
mA
mA
0.075 mW
+0.005 %/%
+0.01 %/%
RAB = 10 kΩ/50 kΩ/100 kΩ
VA = 1 Vrms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V, RAB = 10 kΩ/50
kΩ/100 kΩ
10 kΩ/50 kΩ/100 kΩ, code = midscale,
f = 1 kHz (thermal noise only)
VA = VDD, VB = 0 V, Measure VW with
adjacent RDAC making full scale
change
Signal input at A1 and measure output
at W3, f = 1kHz
400/80/40
0.05
1.5/7/14
9/20/29
-80
-72
kHz
%
µs
nV/√Hz
dB
dB
1 Typical represents the average reading at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ
version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 6 of 28

6 Page









AD5251 pdf, datenblatt
AD5251/AD5252
Table 7. Addresses for Writing (Storing) RDAC Settings and
User-Defined Data to EEMEM Registers (R/W = 0,
CMD/REG = 0, EE/RDAC = 1)
A4 A3 A2 A1 A0 Data Byte Description
0 0 0 0 0 Reserved
0 0 0 0 1 Store RDAC1 setting to
EEMEM11
0 0 0 1 0 Reserved
0 0 0 1 1 Store RDAC3 setting to
EEMEM31
0 0 1 0 0 Store user data to EEMEM4
0 0 1 0 1 Store user data to EEMEM5
0 0 1 1 0 Store user data to EEMEM6
0 0 1 1 1 Store user data to EEMEM7
0 1 0 0 0 Store user data to EEMEM8
0 1 0 0 1 Store user data to EEMEM9
0 1 0 1 0 Store user data to EEMEM10
0 1 0 1 1 Store user data to EEMEM11
0 1 1 0 0 Store user data to EEMEM12
0 1 1 0 1 Store user data to EEMEM13
0 1 1 1 0 Store user data to EEMEM14
0 1 1 1 1 Store user data to EEMEM15
1 User can store any of the 64 RDAC settings for AD5251 or any of the 256
RDAC settings for AD5252.
RDAC/EEMEM Read
The AD5251/AD5252 provide two different RDAC or EEMEM
read operations. For example, Figure 9 shows the method of
reading the RDAC0 to RDAC3 contents without specifying the
address, assuming Address RDAC0 was already selected from
the previous operation. If RDAC_N, other than Address 0, is
selected previously, readback starts with Address N, followed by
N + 1, and so on.
Figure 10 illustrates a random RDAC or EEMEM read
operation. This operation lets users specify which RDAC or
EEMEM register is read by first issuing a dummy write
command to change the RDAC address pointer, and then
proceeding with the RDAC read operation at the new address
location.
Table 8. Addresses for Reading (Restoring) RDAC Settings
and User Data from EEMEM (R/W = 1, CMD/REG = 0,
EE/RDAC = 1)
A4 A3 A2 A1 A0 Data Byte Description
0 0 0 0 0 Reserved
0 0 0 0 1 Read RDAC1 Setting from
EEMEM1
0 0 0 1 0 Reserved
0 0 0 1 1 Read RDAC3 Setting from
EEMEM3
0 0 1 0 0 Read user data from EEMEM4
0 0 1 0 1 Read user data from EEMEM5
0 0 1 1 0 Read user data from EEMEM6
0 0 1 1 1 Read user data from EEMEM7
0 1 0 0 0 Read user data from EEMEM8
0 1 0 0 1 Read user data from EEMEM9
0 1 0 1 0 Read user data from EEMEM10
0 1 0 1 1 Read user data from EEMEM11
0 1 1 0 0 Read user data from EEMEM12
0 1 1 0 1 Read user data from EEMEM13
0 1 1 1 0 Read user data from EEMEM14
0 1 1 1 1 Read user data from EEMEM15
S 0 1 0 1 1AA1A
DD
10
RDAC1
EEMEM OR REGISTER DATA
A RDAC3 A P
EEMEM OR REGISTER DATA
RDAC SLAVE ADDRESS
1 READ
(N BYTES + ACKNOWLEDGE)
Figure 9. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register).
S SLAVE ADDRESS
0A
INSTRUCTION AND
ADDRESS
AS
SLAVE ADDRESS
1A
RDAC OR
EEMEM DATA
A/A P
0 WRITE
REPEATED START
1 READ
Figure 10. RDAC or EEMEM Random Read
(N BYTES + ACKNOWLEDGE)
Rev. 0 | Page 12 of 28

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