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ST24W16 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST24W16
Beschreibung (ST2xxx) 16 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 17 Seiten
ST24W16 Datasheet, Funktion
ST24C16, ST25C16
ST24W16, ST25W16
16 Kbit Serial I2C Bus EEPROM
with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 16 Kbit I2C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
Table 1. Signal Names
PRE
PB0, PB1
SDA
SCL
MODE
WC
VCC
VSS
Write Protect Enable
Protect Block Select
Serial Data Address Input/Output
Serial Clock
Multybyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
VCC
2
PB0-PB1
PRE
SCL
MODE/WC*
ST24x16
ST25x16
SDA
VSS
AI00866B
Note: WC signal is only available for ST24/25W16 products.
February 1999
1/17






ST24W16 Datasheet, Funktion
ST24/25C16, ST24/25W16
Table 7. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Alt
Parameter
Min Max Unit
tCH1CH2
tR Clock Rise Time
1 µs
tCL1CL2
tF Clock Fall Time
300 ns
tDH1DH2
tR Input Rise Time
1 µs
tDL1DL1
tCHDX (1)
tF
tSU:STA
Input Fall Time
Clock High to Input Transition
300 ns
4.7 µs
tCHCL
tHIGH
Clock Pulse Width High
4 µs
tDLCL
tHD:STA
Input Low to Clock Low (START)
4
µs
tCLDX
tHD:DAT
Clock Low to Input Transition
0
µs
tCLCH
tLOW
Clock Pulse Width Low
4.7 µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
250
ns
tCHDH
tSU:STO Clock High to Input High (STOP)
4.7
µs
tDHDL
tCLQV (2)
tBUF Input High to Input Low (Bus Free)
tAA Clock Low to Next Data Out Valid
4.7 µs
0.3 3.5 µs
tCLQX
tDH Data Out Hold Time
300 ns
fC fSCL Clock Frequency
100 kHz
tW (3)
tWR Write Time
10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)
the maximum programming time is doubled to 20ms.
Table 8. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref.
Voltages
50ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION
I2C Bus Background
The ST24/25x16 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x16 are always slave
devices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
6/17

6 Page









ST24W16 pdf, datenblatt
ST24/25C16, ST24/25W16
Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16)
WC
BYTE WRITE
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
NO ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
R/W
NO ACK
NO ACK
DATA IN N
AI01161B
Read Operation
Read operations are independent of the state of the
MODE signal. On delivery, the memory content is
set at all "1’s" (or FFh).
Current Address Read. The memory has an in-
ternal byte address counter. Each time a byte is
read, this counter is incremented. For the Current
Address Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte out-
put, but terminates the transfer with a STOP con-
dition.
Random Address Read. A dummy write is per-
formed to load the address into the address counter
(see Figure 11). This is followed by another START
condition from the master and the byte address
repeated with the RW bit set to ’1’. The memory
acknowledges this and outputs the byte ad-
dressed. The master does NOT acknowledge the
byte output, but terminates the transfer with a
STOP condition.
Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad-
dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se-
quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-
12/17

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