Datenblatt-pdf.com


ID82C237 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ID82C237
Beschreibung CMOS High Performance Programmable DMA Controller
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 25 Seiten
ID82C237 Datasheet, Funktion
82C237
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Fully Compatible with Intersil 82C37A
- 82C237 May be Used in 8MHz and 12.5MHz 82C37A
Sockets
• Optimized for 10MHz and 12.5MHz 80C286 Systems
• Special Mode Permits 16-Bit, Zero Wait State DMA
Transfers
• High Speed Data Transfers:
- Up to 6.25MBytes/sec with 12.5MHz Clock in
Normal Mode
- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit
Mode
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C237 is a modified version of the 82C37A. The
82C237 is fully software and pin for pin compatible with the
82C37A but provides an additional mode for 16-bit DMA
transfers, as well as enhanced speed. Each channel may be
individually programmed for 8-bit or 16-bit data transfers.
The 82C237 controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C237 is designed to be used with an external address
latch, such as the 82C82, to demultiplex the most significant
8 bits of address. An additional latch is required to
temporarily store the most significant 8 bits of data if 16-bit
memory-to-memory transfers are desired. The 82C237 can
be used with industry standard microprocessors such as
80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80,
NSC800, 80186 and others. Multimode programmability
allows the user to select from three basic types of DMA
services, and reconfiguration under program control is
possible even with the clock to the controller stopped. Each
channel has a full 64K address and word count range, and
may be programmed to autoinitialize these registers
following DMA termination (end of process).
Ordering Information
PACKAGE
PDIP
PLCC
SBDIP
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
SMD#
CLCC
SMD#
-55oC to +125oC
8MHz
CP82C237
IP82C237
CS82C237
IS82C237
CD82C237
ID82C237
MD82C237/B
5962-9054304MQA
MR82C237/B
5962-9054304MXA
12.5MHz
CP82C237-12
IP82C237-12
CS82C237-12
IS82C237-12
CD82C237-12
ID82C237-12
MD82C237-12/B
5962-9054305MQA
MR82C237-12/B
5962-9054305MXA
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-148
File Number 2965.1






ID82C237 Datasheet, Funktion
82C237
The 82C237 can assume seven separate states, each
composed of one full CLK period. State I (SI) is the idle
state. It is entered when the 82C237 has no valid DMA
requests pending, at the end of a transfer sequence, or
when a RESET or Master Clear has occurred. While in SI,
the DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).
State 0 (S0) is the first state of a DMA service. The 82C237
has requested a hold but the processor has not yet returned
an acknowledge. The 82C237 may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the READY line on
the 82C237. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the 82C237 in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-memory transfers require a read-from and a write-
to memory to complete each transfer. The States, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four states (S21, S22,
S23, S24) for the write-to-memory half of the transfer.
Idle Cycle
Special software commands can be executed by the 82C237
in the Program Condition. These commands are decoded as
sets of addresses with CS, IOR, and IOW. The commands
do not make use of the data bus. Instructions include Set
and Clear First/Last Flip-Flop, Master Clear, Clear Mode
Register Counter, and Clear Mask Register.
Active Cycle
When the 82C237 is in the Idle cycle, and a software request
or an unmasked channel requests a DMA service, the device
will issue HRQ to the microprocessor and enter the Active
cycle. It is in this cycle that the DMA service will take place,
in one of four modes:
Single Transfer Mode - In single transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
“rolls over” from zero to FFFFH, a terminal count bit in the
status register is set, an EOP pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C237 and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.
When no channel is requesting service, the 82C237 will
enter the idle cycle and perform “SI” States. In this cycle, the
82C237 will sample the DREQ lines on the falling edge of
every CLK cycle to determine if any channel is requesting a
DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
82C237. When CS is low and HLDA is low, the 82C237
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by read-
ing from or writing to the internal registers.
The 82C237 may be programmed with the clock stopped,
provided that HLDA is low and at least one rising CLK edge
has occurred after HLDA was driven low, so the controller is
in an SI state. Address lines A0-A3 are inputs to the device
and select which registers will be read or written. The IOR
and IOW lines are used to select and time the read or write
operations. Due to the number and size of the internal regis-
ters, an internal flip-flop called the First/Last Flip-Flop is
used to generate an additional bit of address. The bit is used
to determine the upper or lower byte of the 16-bit Address
and Work Count registers. The flip-flop is reset by Master
Clear or RESET. Separate software commands can also set
or reset this flip-flop.
Block Transfer Mode - In Block Transfer mode, the device is
activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.
Demand Transfer Mode - In Demand Transfer mode the
device continues making transfers until a TC or external
EOP is encountered, or until DREQ goes inactive. Thus,
transfer may continue until the I/O device has exhausted its
data capacity. After the I/O device has had a chance to catch
up, the DMA service is reestablished by means of a DREQ.
During the time between services when the microprocessor
is allowed to operate, the intermediate values of address and
word count are stored in the 82C237 Current Address and
Current Word Count registers. Higher priority channels may
intervene in the demand process, once DREQ has gone
inactive. Only an EOP can cause an Autoinitialization at the
end of service. EOP is generated either by TC or by an
external signal.
Cascade Mode - This mode is used to cascade more than
one 82C237 for simple system expansion. The HRQ and
HLDA signals from the additional 82C237 are connected to
the DREQ and DACK signals respectively of a channel for
4-153

6 Page









ID82C237 pdf, datenblatt
82C237
If an active channel is cascaded, as defined by its mode reg-
ister, DWLE will be driven low at the start of the transfer, and
will remain low for the entire transfer. This allows the DWLE
signal from the slave 82C237 to control the system. To form
the system DWLE signal for cascaded 82C237s, simply “OR”
the individual DWLE outputs of the Master and Slaves.
or 16-bit transfers. Data bits 4-7 represent DREQ channels 0-
3 respectively and determine the data width (8-bit or 16-bit) of
each channel during DMA transfers. When programming this
register, bit 3 of the data must be set to “0”. Since the address
of the Data-Width register is the same as the Mask register,
bit 3 selects which register is actually written.
Registers Affected by 16-Bit
Transfer Mode
Data-Width Register - 16-bit transfer mode enabled
76543210
BIT NUMBER
Current Address Register - Each channel has a 16-bit Cur-
rent Address register. This register holds the value of the
address used during DMA transfers. On channels pro-
grammed to perform 8-bit DMA transfers, the address is
automatically incremented or decremented by one after
each transfer. On channels programmed for 16-bit DMA
transfers, the address is automatically incremented or decre-
mented by two after each transfer.
During all 16-bit transfers, the A0 output will remain low for
the entire transfer, even if an odd address is programmed
into the channel’s Current Address register (i.e. only even
word addresses will be generated).
The Current Address register is written or read by the micro-
processor in successive 8-bit bytes. See Figure 6 for pro-
gramming information. It may also be reinitialized by an
Autoinitialize back to its original value. Autoinitialize takes
place only after an EOP. In memory-to-memory mode, the
channel 0 Current Address register can be prevented from
incrementing or decrementing by setting the address hold bit
in the Command register.
Current Word Count Register - Each channel has a 16-bit
Current Word Count register. This register determines the
number of transfers to be performed. On channels pro-
grammed for 8-bit transfers, the actual number of transfers
will be one more than the number programmed in the Cur-
rent Word Count register (i.e. programming a count of 100
will result in 101 transfers). The word count is decremented
by one after each transfer on 8-bit transfer channels.
On channels programmed for 16-bit transfers, the word
count is decremented by two after each transfer. This means
that for even values in the Current Word Count register, the
actual number of transfers will be n/2 + 1, where n is the
value in the Current Word Count register. For odd values in
this register, the actual number of transfers will be (n+1)/2.
When the value in the Current Word Count register decre-
ments past zero (i.e. 0 to FFFEH or 1 to FFFFH), a TC will
be generated.
This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC on 8-bit transfers, or
FFFEH after TC on 16-bit transfers.
Data-Width Register - When 16-bit transfer mode is enabled,
the Data-Width register becomes accessible and is used to
program each DMA channel to perform either 8-bit transfers
X Don’t Care
0 Must be 0 to write all
data - width bits
0 Channel 0 = 16-bit transfers
1 Channel 0 = 8-bit transfers
0 Channel 1 = 16-bit transfers
1 Channel 1 = 8-bit transfers
0 Channel 2 = 16-bit transfers
1 Channel 2 = 8-bit transfers
0 Channel 3 = 16-bit transfers
1 Channel 3 = 8-bit transfers
Mask Register - In 16-bit transfer mode this register oper-
ates the same as the previous Mask register description with
the exception of bit 3 when writing the instruction to sepa-
rately set or clear a mask bit. Bit 3 of the data must be “1”
when writing a single mask bit. Bits 4-7 are ignored when
this instruction is written. Refer to the following diagram for
writing single mask bits.
Mask Register - 16-bit transfer mode enabled
76543210
BIT NUMBER
Don’t Care
00 Select channel 0 mask bit
01 Select channel 1 mask bit
10 Select channel 2 mask bit
11 Select channel 3 mask bit
0 Clear mask bit
1 Set mask bit
1 Must be 1 to write single
mask bit
The software command to write all four bits of the Mask reg-
ister has no effect on the state of the Data-Width bits.
When reading the Mask/Data-Width register (they share the
same address), bits 0-3 will always display the mask bits of
channels 0-3, respectively. With 16-bit transfer mode not
enabled, bits 4-7 will always read as logical ones. With 16-bit
transfer mode enabled, bits 4-7 will display the data-width
bits for channels 0-3 respectively.
The Mask and Data-Width registers are set by RESET or
Master Clear. This disables all hardware DMA requests until
a clear mask bit instruction allows them to be recognized.
RESET or Master Clear forces the Mask and Data-Width
4-159

12 Page





SeitenGesamt 25 Seiten
PDF Download[ ID82C237 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ID82C237CMOS High Performance Programmable DMA ControllerIntersil Corporation
Intersil Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche