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ID82C85 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ID82C85
Beschreibung CMOS Static Clock Controller/Generator
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 20 Seiten
ID82C85 Datasheet, Funktion
82C85
March 1997
CMOS Static Clock Controller/Generator
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors and Peripherals
• Complete Control Over System Operation for Very
Low System Power
- Stop-Oscillator
- Low Frequency
- Stop-Clock
- Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC
Package Options
• Single 5V Power Supply
• Operating Temperature Range
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NUMBER
CS82C85
IS82C85
CD82C85
ID82C85
MD82C85/B
MR82C85/B
PACKAGE
28 Ld PLCC
24 Ld CERDIP
28 Pad CLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
N28.45
N28.45
F24.3
F24.3
F24.3
J28.A
The Intersil 82C85 Static CMOS Clock Controller/Genera-
tor provides complete control of static CMOS system oper-
ating modes and supports full speed, slow, stop-clock and
stop-oscillator operation. While directly compatible with the
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-
sor Family, the 82C85 can also be used for general system
clock control.
For static system designs, separate signals are provided on
the 82C85 for stop (S0, S1, S2/STOP) and start (START)
control of the crystal oscillator and system clocks. A single
control line (SLO/FST) determines 82C85 fast (crystal/EFI
frequency divided by 3) or slow (crystal/EFI frequency
divided by 768) mode operation. Automatic maximum
mode 80C86 and 80C88 software HALT instruction decode
logic in the 82C85 enables software-based clock control.
Restart logic insures valid clock start-up and complete syn-
chronization of system clocks.
The 82C85 is manufactured using the Intersil advanced
Scaled SAJI IV CMOS process. In addition to clock control
circuitry, the 82C85 also contains a crystal controlled
oscillator (up to 25MHz), clock generation logic, complete
“Ready” synchronization and reset logic. This permits the
designer to tailor the system power-performance product to
provide optimum performance at low power levels.
Pinouts
24 LEAD CERDIP
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 VCC
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
28 LEAD PLCC, CLCC
TOP VIEW
4 3 2 1 28 27 26
RDY1 5
25 NC
READY 6
24 ASYNC
RDY2 7
23 EFI
AEN2 8
22 F/C
CLK 9
21 OSC
GND 10
20 RES
NC 11
19 RESET
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-297
File Number 2976.1






ID82C85 Datasheet, Funktion
82C85
FAST mode operation is enabled by each of two conditions:
• The SLO/FST input is HIGH and a START or reset
command is issued
• The SLO/FST input is held HIGH for at least 6 oscillator or
EFI cycles.
Alternate Operating Modes
Using alternate modes of operation (slow, stop-clock, stop-
oscillator) will reduce the average system operating power
dissipation in a static CMOS system (See Table 2). This
does not mean that system speed or throughput must be
reduced. When used appropriately, the slow, stopclock, stop-
oscillator modes can make your design more power efficient
while maintaining maximum system performance.
Stop-Oscillator Mode
When the 82C85 is stopped while in the crystal mode (F/C
LOW), the oscillator, in addition to all system clock signals
(CLK, CLK50 and PCLK), are stopped. CLK and CLK50 stop
in the high state. PCLK stops in it’s current state (high or low).
With the oscillator stopped, 82C85 power drops to it’s lowest
level. All clocks and oscillators are stopped. All devices in
the system which are driven by the 82C85 go into the lowest
power standby mode. The 82C85 also goes into standby and
requires a power supply current of less than 100µA.
Stop-Clock Mode
When the 82C85 is in the EFI mode (F/C HIGH) and a STOP
command is issued, all system clock signals (CLK, CLK50,
and PCLK) are stopped. CLK and CLK50 stop in the high
state when F/C is low and may stop in either the high or low
state when F/C is high. PCLK stops in its current state (high
or low).
The 82C85 can also provide it’s own EFI source simply by
connecting the OSC output to the EFI input and pulling the
F/C input HIGH. This puts the 82C85 into the External Fre-
quency Mode using it’s own oscillator as an external source
signal (See Figure 2). In this configuration, when the 82C85
is stopped in the EFI mode, the oscillator continues to run.
Only the clocks to the CPU and peripherals (CLK, CLK50
and PCLK) are stopped.
Oscillator/Clock Stop Operation
Three control lines determine when the 82C85 clock outputs
or oscillator will stop. These are S0, S1 and S2/STOP. These
three lines are designed to connect directly to the MAXimum
mode 80C86 and 80C88 status lines or to be driven by exter-
nal I/O signals (such as an 82C55A output port).
In the MAXimum mode configuration, the 82C85 will auto-
matically recognize a software HALT command from the
80C86 or 80C88 and stop the system clocks or oscillator.
This allows complete software control of the STOP function.
If the 80C86 or 80C88 is used in the MINimum mode, the
82C85 can be controlled using the S2/STOP input (with S0
and S1 held high). This can be done using an external I/O
control line, such as from an 82C55A or by decoding the
state of the 80C86 MINimum mode status signals.
82C85 status inputs S2/STOP, S1, S0 are sampled on the
rising edge of CLK. The oscillator (F/C LOW only) and clock
outputs are stopped by S2/STOP, S1, S0 being in the LHH
state on a low-to-high transition of CLK. This LHH state must
follow a passive HHH state occurring on the previous low-to-
high CLK transition. CLK and CLK50 will stop in the logic
HIGH state after two additional complete cycles of CLK.
PCLK stops in it’s current state (HIGH or LOW). This is true
for both SLOW and FAST mode operation.
80C86/88 Maximum Mode Clock Control
The 82C85 STOP function has been optimized for 80C86/88
MAXimum mode operation. In this mode, the three 82C85 sta-
tus inputs (S2/STOP, S1, S0) are connected directly to the
MAXimum mode status lines (S2, S1, S0) of the Intersil
80C86 or 80C88 static CMOS microprocessors (See Figure
3).
When in the MAXimum mode, the 80C86/88 status lines
identify which type of bus cycle the CPU is starting to exe-
cute. 82C85 S2/STOP, S1 and S0 control input logic will rec-
ognize a valid MAXimum mode software HALT executed by
the 80C86 or 80C88. Once this state has been recognized,
the 82C85 stops the clock (F/C HIGH) and oscillator (F/C
LOW) operation.
VCC
X1
EFI
X2
OSC
STOP
CONTROL
F/C
S2/STOP
S1 START
S0
START
CONTROL
FIGURE 2. STOP-CLOCK MODE USING 82C85 IN EFI MODE
WITH OSCILLATOR AS FREQUENCY SOURCE
S2
S1
S0
MN/MX
80C86/88
S2/STOP
S1
S0
82C85
FIGURE 3. 82C85 STOP CONTROL USING 80C86/88
MAXIMUM MODE STATUS LINES
4-302

6 Page









ID82C85 pdf, datenblatt
82C85
AC Electrical Specifications
VCC = 5V ±10%;TA = 0oC to +70oC (C82C85);
TA = -40oC to +85oC (I82C85);
TA = -55oC to +125oC (M82C85)
LIMITS
(Continued)
SYMBOL
PARAMETER
MIN
MAX
UNITS
CONDITIONS
(27) TCLCH
CLK LOW Time
(2/3 TCLCL)-15
-
ns
(28) T5CHCL
CLK50 HIGH Time
(1/2 TCLCL)-7.5
-
ns
(29) T5CLCH
CLK50 LOW Time
(1/2 TCLCL)-7.5
-
ns
(30) TCH1CH2 CLK/CLK50 Rise Time
- 8 ns 1.0V to 3.5V
(31) TCL2CL1 CLK/CLK50 Fall Time
- 8 ns 1.0V to 3.5V
(32) TPHPL
PCLK HIGH Time
TCLCL-20 - ns
(33) TPLPH
PCLK LOW Time
TCLCL-20 - ns
(34) TRYLCL
Ready Inactive to CLK
-8 - ns Note 4
(35) TRYHCH
Ready Active to CLK
2/3(TCLCL)-15
-
ns Note 3
(36) TCLIL
CLK to Reset Delay
- 40 ns
(37) TCLPH
CLK to PCLK HIGH Delay
- 22 ns
(38) TCLPL
CLK to PCLK LOW Delay
- 22 ns
(39) TOST
Start/Reset Valid to Clock LOW
- 2 ms Typ. - Note 8
(40) TOLOH
Output Rise Time (except CLK)
- 15 ns From 0.8V to 2.0V
(41) TOHOL
Output Fall Time (except CLK)
- 12 ns From 2.0V to 0.8V
(42) TRST
RESET output HIGH Time
16 x TCLCL
-
ns
(43) TCLC50L CLK LOW to CLK50 LOW Skew
- 5 ns
NOTES:
1. Slow and Fast Modes.
2. Setup and hold necessary only to guarantee recognition at next clock.
3. Applies only to T3, TW states.
4. Applies only to T2 states.
5. All timing delays are measured at 1.5V unless otherwise noted.
6. Input signals must switch between VIL max - 0.4 and VIH min + 0.4 volts
7. Timing measurements made with EFI duty cycle = 50%.
8. Oscillator start up time depends on several factors including crystal frequency, crystal manufacturer, capacitive load, temperature, power
supply voltage, etc. This parameter is given for information only.
9. Output signals switch between VOH and VOL unless otherwise specified.
4-308

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