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UDA1334BTS Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UDA1334BTS
Beschreibung Low power audio DAC
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
UDA1334BTS Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
UDA1334BTS
Low power audio DAC
Preliminary specification
File under Integrated Circuits, IC01
2000 Feb 07






UDA1334BTS Datasheet, Funktion
Philips Semiconductors
Low power audio DAC
Preliminary specification
UDA1334BTS
7 PINNING
SYMBOL PIN
PAD TYPE
BCK
1 5 V tolerant digital input pad; note 1
WS 2 5 V tolerant digital input pad; note 1
DATAI
3 5 V tolerant digital input pad; note 1
VDDD
VSSD
SYSCLK
4 digital supply pad
5 digital ground pad
6 5 V tolerant digital input pad; note 1
SFOR1
7 5 V tolerant digital input pad; note 1
MUTE
8 5 V tolerant digital input pad; note 1
DEEM
9 5 V tolerant digital input pad; note 1
PCS
10 3-level input pad; note 2
SFOR0
11 digital input pad; note 2
Vref(DAC)
VDDA
VOUTL
12 analog pad
13 analog supply pad
14 analog output pad
VSSA
VOUTR
15 analog ground pad
16 analog output pad
DESCRIPTION
bit clock input
word select input
serial data input
digital supply voltage
digital ground
system clock input
serial format select 1
mute control
de-emphasis control
power control and sampling frequency select
serial format select 0
DAC reference voltage
DAC analog supply voltage
DAC output left
DAC analog ground
DAC output right
Notes
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages
this is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.
2000 Feb 07
handbook, halfpage
BCK 1
16 VOUTR
WS 2
DATAI 3
15 VSSA
14 VOUTL
VDDD 4
13 VDDA
UDA1334BTS
VSSD 5
12 Vref(DAC)
SYSCLK 6
11 SFOR0
SFOR1 7
10 PCS
MUTE 8
9 DEEM
MGL963
Fig.2 Pin configuration.
6

6 Page









UDA1334BTS pdf, datenblatt
Philips Semiconductors
Low power audio DAC
Preliminary specification
UDA1334BTS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IDDD
digital supply current
normal operating mode
at 2.0 V supply voltage
at 3.0 V supply voltage
1.4
2.1
mA
mA
Sleep mode;
at 2.0 V supply voltage
clock running
no clock running
Sleep mode;
at 3.0 V supply voltage
clock running
no clock running
250
20
375
30
µA
µA
µA
µA
Digital input pins; note 2
VIH HIGH-level input voltage at 2.0 V supply voltage 1.3
at 3.0 V supply voltage 2.0
VIL LOW-level input voltage at 2.0 V supply voltage 0.5
at 3.0 V supply voltage 0.5
ILIinput leakage current
Ci input capacitance
3.3 V
5.0 V
+0.5 V
+0.8 V
1 µA
10 pF
3-level input: pin PCS
VIH HIGH-level input voltage
VIM MID-level input voltage
VIL LOW-level input voltage
0.9VDDD
0.4VDDD
0.5
VDDD + 0.5
0.6VDDD
+0.5
V
V
V
DAC
Vref(DAC)
Ro(ref)
Io(max)
reference voltage
output resistance on
pin Vref(DAC)
maximum output current
RL load resistance
CL load capacitance
with respect to VSSA
(THD + N)/S < 0.1%;
RL = 800
note 3
0.45VDDA
0.5VDDA
12.5
tbf
3
−−
0.55VDDA
V
k
mA
k
50 pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.
3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent
oscillations in the output operational amplifier.
2000 Feb 07
12

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