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UDA1335H Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UDA1335H
Beschreibung Universal Serial Bus USB Audio Playback Recording Peripheral APRP
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
UDA1335H Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
UDA1335H
Universal Serial Bus (USB) Audio
Playback Recording Peripheral
(APRP)
Preliminary specification
File under Integrated Circuits, IC01
1998 Aug 28






UDA1335H Datasheet, Funktion
Philips Semiconductors
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
Preliminary specification
UDA1335H
PINNING
SYMBOL
GP3/WSO
GP4/BCKO
P0.5
SHTCB
P0.6
D
P0.7
D+
VDDI
VSSI
VSSE
VDDE
GP1/DI
P2.0
GP5/WSI
P2.1
GP0/BCKI
P2.2
SCL
P2.3
SDA
P2.4
P2.5
VSSX
XTAL1b
XTAL2b
CLK
VDDX
P2.6
P2.7
PSEN
VDDO
VSSO
VOUTL
TC
RTCB
VOUTR
VDDA1
VSSA1
PIN
QFP64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1998 Aug 28
I/O DESCRIPTION
I/O general purpose pin 3 or word select output
I/O general purpose pin 4 or bit clock output
I/O port 0.5 of the microcontroller
I shift clock of the test control block (active HIGH)
I/O port 0.6 of the microcontroller
I/O negative data line of the differential data bus, conforms to the USB standard
I/O port 0.7 of the microcontroller
I/O positive data line of the differential data bus, conforms to the USB standard
digital supply voltage for core
digital ground for core
digital ground for I/O pads
digital supply voltage for I/O pads
I/O general purpose pin 1 or data input
I/O port 2.0 of the microcontroller
I/O general purpose pin 5 or word select input
I/O port 2.1 of the microcontroller
I/O general purpose pin 0 or bit clock input
I/O port 2.2 of the microcontroller
I/O serial clock line I2C-bus
I/O port 2.3 of the microcontroller
I/O serial data line I2C-bus
I/O port 2.4 of the microcontroller
I/O port 2.5 of the microcontroller
crystal oscillator ground (48 MHz)
I crystal input (analog; 48 MHz)
O crystal output (analog; 48 MHz)
O 48 MHz clock output signal
supply crystal oscillator (48 MHz)
I/O port 2.6 of the microcontroller
I/O port 2.7 of the microcontroller
I/O program store enable (active LOW)
supply voltage for operational amplifier
operational amplifier ground
O voltage output left channel
I test control input (active HIGH)
I asynchronous reset input of the test control block (active HIGH)
O voltage output right channel
analog supply voltage 1
analog ground 1
6

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UDA1335H pdf, datenblatt
Philips Semiconductors
Universal Serial Bus (USB) Audio
Playback Recording Peripheral (APRP)
Preliminary specification
UDA1335H
The Asynchronous Digital-to-Analog Converter
(ADAC)
The ADAC receives USB audio information from the USB
processor or from the digital I/O-bus. The ADAC is able to
reconstruct the sample clock from the rate at which the
audio samples arrive and handles the audio sound
processing. After the processing, the audio signal is
upsampled, noise-shaped and converted to analog output
voltages capable of driving a line output. The ADAC
consists of:
A Sample Frequency Generator (SFG)
FIFO registers
An audio feature processing DSP
Two digital upsampling filters and a variable hold
register
A digital Noise Shaper (NS)
A Filter Stream DAC (FSDAC) with integrated filter and
line output drivers.
The Sample Frequency Generator (SFG)
The SFG controls the timing signals for the asynchronous
digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the upsampling
filters.
First-In First-Out (FIFO) registers
The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO (in conjunction with the
SFG) is necessary to remove all jitter present on the
incoming audio signal.
The audio feature processing DSP
A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the USB APRP”. Depending on the sampling
rate (fs) the DSP knows four frequency domains in which
the treble and bass are regulated. The domain is chosen
automatically.
Table 5 Frequency domains for audio processing by the
DSP
DOMAIN
1
2
3
4
SAMPLE FREQUENCY (kHz)
5 to 12
12 to 25
25 to 40
40 to 55
The upsampling filters and variable hold function
After the audio feature processing DSP two upsampling
filters and a variable hold function increase the
oversampling rate to 128fs.
The noise shaper
A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.
The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.
USB Audio Playback Recording Peripheral (APRP)
descriptors
In a typical USB environment the PC has to know which
kind of devices are connected. For this purpose each
device contains a number of USB descriptors. These
descriptors describe, from different points of view (USB
configuration, USB interface and USB endpoint), the
capabilities of a device. Each of them can be requested by
the host. The collection of descriptors is denoted as a
descriptor map. This descriptor map will be reported to the
USB host during enumeration and on request.
The USB descriptors and their most important fields, in
relationship to the characteristics of the UDA1335H are
explained briefly below.
1998 Aug 28
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