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W83194BR-B Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194BR-B
Beschreibung Stepless Clock Gen For INTEL Brookdale Chipset
Hersteller Winbond
Logo Winbond Logo 




Gesamt 19 Seiten
W83194BR-B Datasheet, Funktion
W83194BR-B
Stepless Clock Gen. For INTEL
Brookdale Chipset
Date: 02/25/2003 Revision: 2.0






W83194BR-B Datasheet, Funktion
W83194BR-B
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
3. PIN CONFIGURATION
VDDREF
XIN
XOUT
GND
FS0& /PCICLK_F1^
FS1& /PCICLK_F2^
VDDPCI
GND
ENW D*/PCICLK0^
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
RESET#
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF^/FS2&
47 CPUCLKT0
46 CPUCLKC0
45 VDDCPU
44 CPUCLKT1
43 CPUCLKC1
42 GND
41 VDDCPU
40 CPUCLKT2
39 CPUCLKC2
38 M ULTISEL0*
37 IREF
36 GND
35 48M HZ_USB /FS3&
34 48M HZ_DOT
33 AVDD48
32 GND
31 3V66_0/VCH_CLK /FS4&
30 VDD3V66
29 GND
28 SCLK*
27 SDATA*
26 VTT_PW RGD /PD#*
25 GND
#: Active low
^: These outputs have 1.5 ~ 2X drive strength
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
X IN
XOUT
V T T _PW R G D
F S < 0 :4 >
PD #*
M U L T SE L 0*
SD A TA *
SC LK *
PL L 2
X TA L
O SC
PL L 1
S p read
S p ectru m
V CO CLK
M /N /R atio
RO M
L atch
& PO R
C o n tro l
L o g ic
& C o n fig
R eg ister
I2 C
In terface
D iv id er
D iv id er
2
48M H z
R EF^
3
C P U C L K _ T 0 :2
3 C P U C L K _ C 0 :2
1 3V 66_0/
V C H _C L K
3
3 V 6 6 _ 1 :3
9 P C IC L K _ 0 :6
P C IC L K _ F 1 :2
R ESET#
R ref
Publication Release Date: February 2003
- 2 - Revision 2.0

6 Page









W83194BR-B pdf, datenblatt
W83194BR-B
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
7.4 Register 3: PCI, 48MHz Clock Register (1 = Enable, 0 = Stopped)
Bit Pin NO PWD Description
7 34 1 48MHZ_DOT
6 35 1 48MHZ_USB
5 48 1 REF
4 - 1 Reserved
3 EN_VCH_CLK 0 1 = VCH_CLK 48MHz clock output.
0 = 3V66_0 66MHz clock output (default).
2 - 1 Reserved
1 6 1 PCICLK_F1
0 5 1 PCICLK_F0
7.5 Register 4: 3V66 Control Register (1 = Enable, 0 = Stopped)
Bit Pin NO PWD Description
7 - 1 Reserved
6 - 1 Reserved
5 - 1 Reserved
4 - 1 Reserved
3 22 1 3V66_3
2 21 1 3V66_2
1 20 1 3V66_1
0 31 1 3V66_0/VCH_CLK
7.6 Register 5: Watchdog Control Register
Bit
Name
PWD Description
7
Reserved
0 Reserved
X Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer.
6 EN_WD
This bit is trapping pin during VTT_PWRGD#. Read this bit will return a
counting state. If timer continues down count, this bit will return 1.
Otherwise, this bit will return 0.
0 Watchdog Timeout Status. If the watchdog is started and timer down
5 WD_TIMEOUT
counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1,
when the watchdog is restart in the next time. This bit is Read Only.
4 SAF_FREQ [4] 0
3 SAF_FREQ [3] 0
2
SAF_FREQ [2]
0
Watchdog safe frequency bits. These bits will be reloaded into FS [4:0],
if the watchdog is timeout and enable reload safe frequency bits.
1 SAF_FREQ [1] 0
0 SAF_FREQ [0] 0
Publication Release Date: February 2003
- 8 - Revision 2.0

12 Page





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