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PDF LT1371IR Data sheet ( Hoja de datos )
| Número de pieza | LT1371IR | |
| Descripción | 500kHz High Efficiency 3A Switching Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT1371
500kHz High Efficiency
3A Switching Regulator
FEATURES
s Faster Switching with Increased Efficiency
s Uses Small Inductors: 4.7µH
s All Surface Mount Components
s Low Minimum Supply Voltage: 2.7V
s Quiescent Current: 4mA Typ
s Current Limited Power Switch: 3A
s Regulates Positive or Negative Outputs
s Shutdown Supply Current: 12µA Typ
s Easy External Synchronization
U
APPLICATIONS
s Boost Regulators
s Laptop Computer Supplies
s Multiple Output Flyback Supplies
s Inverting Supplies
DESCRIPTION
The LT®1371 is a monolithic high frequency current mode
switching regulator. It can be operated in all standard
switching configurations including boost, buck, flyback,
forward, inverting and “Cuk.” A 3A high efficiency switch
is included on the die, along with all oscillator, control and
protection circuitry.
The LT1371 typically consumes only 4mA quiescent
current and has higher efficiency than previous parts.
High frequency switching allows for very small inductors
to be used.
New design techniques increase flexibility and maintain
ease of use. Switching is easily synchronized to an exter-
nal logic level source. A logic low on the Shutdown pin
reduces supply current to 12µA. Unique error amplifier
circuitry can regulate positive or negative output voltage
while maintaining simple frequency compensation tech-
niques. Nonlinear error amplifier transconductance re-
duces output overshoot on start-up or overload recovery.
Oscillator frequency shifting protects external compo-
nents during overload conditions.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
5V to 12V Boost Converter
ON
OFF
+ C1**
22µF
25V
5V L1*
4.7µH
VIN
S/S VSW
LT1371
FB
GND VC
C2
0.047µF
R3
2k
D1
MBRS330T3
R1
53.6k
1%
VOUT†
12V
+
R2
6.19k
1%
C3
0.0047µF
LT1371 • TA01
C4**
22µF
25V
×2
*COILCRAFT DO3316P-472 (4.7µH),
DO3316P-103 (10µH) OR
SUMIDA CD104-100MC (10µH)
**AVX TPSD226M025R0200
†MAX IOUT
L1 IOUT
4.7µH 0.7A
10µH 0.8A
12V Output Efficiency
100
VIN = 5V
90
80
70
60
50
0.01
0.1
OUTPUT CURRENT (A)
1
LT1371 • TA02
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
VC Pin Threshold and High
Clamp Voltage vs Temperature
2.4
2.2
2.0 VC HIGH CLAMP
1.8
1.6
1.4
1.2
VC THRESHOLD
1.0
0.8
0.6
0.4
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
LT1371 • G10
Feedback Input Current
vs Temperature
800
700 VFB =VREF
600
500
400
300
200
100
0
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
LT1371 • G11
LT1371
Negative Feedback Input Current
vs Temperature
0
VNFB =VNFR
–10
–20
–30
–40
–50
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
LT1371 • G12
PIN FUNCTIONS
VC: The Compensation pin is used for frequency compen-
sation, current limiting and soft start. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground.
FB: The Feedback pin is used for positive output voltage
sensing and oscillator frequency shifting. It is the invert-
ing input to the error amplifier. The noninverting input of
this amplifier is internally tied to a 1.245V reference. Load
on the FB pin should not exceed 250µA when NFB pin is
used. See Applications Information.
NFB: The Negative Feedback pin is used for negative
output voltage sensing. It is connected to the inverting
input of the negative feedback amplifier through a 100k
source resistor.
S/S (R and T7 Packages Only): Shutdown and Synchroni-
zation Pin. The S/S pin is logic level compatible. Shutdown
is active low and the shutdown threshold is typically 1.3V.
For normal operation, pull the S/S pin high, tie it to VIN or
leave it floating. To synchronize switching, drive the S/S
pin between 600kHz and 800kHz.
SHDN: (SW Package Only): The Shutdown pin is active
low and the shutdown threshold is typically 1.3V. For
normal operation, pull the SHDN pin high, tie it to VIN or
leave it floating.
SYNC (SW Package Only): To synchronize switching,
drive the SYNC pin between 600kHz and 800kHz. If not
used, the SYNC pin can be tied high, low or left floating.
VIN: Bypass Input Supply pin with a low ESR capacitor,
10µF or more. The regulator goes into undervoltage lock-
out when VIN drops below 2.5V. Undervoltage lockout
stops switching and pulls the VC pin low.
VSW: The Switch pin is the collector of the power switch
and has large currents flowing through it. Keep the traces
to the switching components as short as possible to
minimize radiation and voltage spikes.
GND: Tie all Ground pins to a good quality ground plane.
5
5 Page 
UU W U
APPLICATIO S I FOR ATIO
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor on the VC pin reduces
switching frequency ripple to only a few millivolts. A low
value for RC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
Layout Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
short as possible. Figures 3, 4 and 5 show recommended
positions for these components. E field radiation is kept
low by minimizing the length and area of all traces con-
nected to the Switch pin. A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
LT1371
CONNECT
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE.
TAB MAY BE
SOLDERED OR
BOLTED TO
GROUND PLANE*
FB GND S/S
VC NFB VSW VIN
D
C
C
KEEP PATH FROM
VSW, OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
*SEE T7 PACKAGE LAYOUT CONSIDERATIONS FOR VERTICAL MOUNTING
OF THE T7 PACKAGE
LT1371 • F04
Figure 4. Layout Considerations— T7 Package
VC
FB
NFB
GND
GND
GND
GND
SHDN
SYNC
VIN
VSW
NC
VSW
GND
GND
GND
GND
NC
NC
GND
D
C
C
KEEP PATH FROM
VSW, OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
CONNECT
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE
FB GND S/S
VC NFB VSW VIN
D
C
C
KEEP PATH FROM
VSW, OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
LT1371 • F03
Figure 3. Layout Considerations— R Package
CONNECT ALL GROUND PINS TO GROUND PLANE
LT1371 • F05
Figure 5. Layout Considerations— SW Package
SWITCH
L1 NODE
VOUT
HIGH
VIN
FREQUENCY
LOAD
CIRCULATING
PATH
Figure 6
LT1371 • F06
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LT1371IR.PDF ] | |
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