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PDF SI3014 Data sheet ( Hoja de datos )
| Número de pieza | SI3014 | |
| Descripción | (SI3014/24.38) Global MC97 Silicon DAA | |
| Fabricantes | Silicon Laboratories | |
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Si3038
GLOBAL MC’97 SILICON DAA
Features
Complete DAA includes:
AC’97 2.1 Compliant
Primary or Secondary Codec
Global Phone Line Interface
Compliant with FCC, CTR21,
JATE, and Other PTTs
84 dB Dynamic Range TX/RX
Paths
3.3 V or 5 V Power Supply
Greater than 3000 V Isolation
Integrated Ring Detector
Wake-Up On Ring
Caller ID Support
Integrated Analog Front End
2- to 4-Wire Hybrid
Low-Power Standby Mode
Low Profile SOIC Packages
Patented ISOcap™ Technology
Applications
Software Modems
Audio/Telephony Sub-Systems
Audio/Modem Riser Cards (AMR)
Mobile Daughter Cards (MDC)
Mini-PCI Cards
Description
The Si3038 is an integrated direct access arrangement (DAA) chipset that
provides a digital, programmable line interface to meet global telephone
line requirements. Available in two 16-pin small outline packages (AC’97
interface on Si3024 and phone-line interface on Si3014), the chipset
eliminates the need for an analog front end (AFE), an isolation
transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3038
dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The
Si3024 complies with the AC’97 2.1 specification.
Functional Block Diagram
XOUT
MCLK/XIN
RESET
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
ID0
ID1
G P IO _A
G P IO _B
Si3024
Clock
AC'97
Digital
Interface
Isolation
Interface
Control
Interface
Si3014
Isolation
Interface
Hybrid
and
DC
Termination
Ring Detect
Off-Hook
RX
FILT
FILT2
REF
DCT
VREG
VREG2
REXT
REXT2
RNG1
RNG2
QB
QE
QE2
Ordering Information:
See page 59.
Pin Assignments
Si3024 (SOIC)
MCLK/XIN
XOUT
BIT_CLK
VD
SDA TA _IN
SDA TA _OUT
SY NC
RESET
1
2
3
4
5
6
7
8
16 GPIO_A
15 GPIO_B
14 ID1
13 VA
12 GND
11 C1A
10 ID0
9 A OUT
Si3024 (TSSOP)
SDA TA _IN
SDA TA _OUT
SY NC
RESET
A OUT
ID0
C1A
GND
1
2
3
4
5
6
7
8
16 V D
15 BIT_CLK
14 XOUT
13 MCLK/XIN
12 GPIO_A
11 GPIO_B
10 ID1
9 VA
Si3014 (SOIC or TSSOP)
QE2
DCT
IGND
C1B
RNG1
RNG2
QB
QE
1
2
3
4
5
6
7
8
16 FILT2
15 FILT
14 RX
13 REXT
12 REXT2
11 REF
10 V REG2
9 V REG
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
Rev. 2.01 9/01
Copyright © 2001 by Silicon Laboratories
Si3038-DS201
1 page  
Si3038
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 0 to 70°C, See Figure 1)
Parameter
Symbol
Test Condition
Min Typ Max Unit
DC Termination Voltage
VTR IL = 20 mA, ACT=1 — — 7.5 V
DCT=11 (CTR21)
DC Termination Voltage
VTR IL = 42 mA, ACT=1 —
DCT=11 (CTR21)
— 14.5 V
DC Termination Voltage
VTR IL = 50 mA, ACT=1 — — 40
DCT=11 (CTR21)
V
DC Termination Voltage
VTR IL = 60 mA, ACT=1 40
—
—
V
DCT=11 (CTR21)
DC Termination Voltage
VTR IL = 20 mA, ACT=0 — — 6.0 V
DCT=01 (Japan)
DC Termination Voltage
VTR IL = 100 mA, ACT=0 11
—
—
V
DCT=01 (Japan)
DC Termination Voltage
VTR IL = 20 mA, ACT=0 — — 7.5 V
DCT=10 (FCC)
DC Termination Voltage
VTR IL = 100 mA, ACT=0 12
—
—
V
DCT=10 (FCC)
On Hook Leakage Current
Operating Loop Current
Operating Loop Current
DC Ring Current
ILK
VTR = -48V
— — 1 µA
ILP FCC/JATE Mode 13 — 120 mA
ILP
CTR21 Mode
13 — 60 mA
w/o Caller ID
— — 20 µA
DC Ring Current
Ring Detect Voltage1
Ring Detect Voltage1
Ring Frequency
Ringer Equivalence Number2
Ringer Equivalence Number2
VRD
VRD
FR
REN
REN
with Caller ID
RT = 0
RT = 1
w/o Caller ID
with Caller ID
— 450 —
µA
11 — 22 VRMS
17 — 33 VRMS
15 — 68 Hz
— — 0.2
— 0.8 —
Notes:
1. The ring signal is guaranteed not to be detected below the minimum and is guaranteed to be detected above the
maximum.
2. C15, R14, Z2, and Z3 not installed. See "Ringer Impedance" on page 25.
TIP +
600 Ω
Si3014 VTR
RING –
10 µF
IL
Note: The remainder of the circuit is identical to the one shown in Figure 19 on page 16.
Figure 1. Test Circuit for Loop Characteristics
Rev. 2.01
5
5 Page 
Table 12. AC Link Timing Characteristics— Low Power Mode Timing
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25°C, CL = 50 pF)
Parameter
Symbol
Min
Typ
End of Slot 2 to BIT_CLK, SDATA_IN
Low
Ts2_pdown
—
—
Si3038
Max
Unit
1.0 µs
SYNC Slot 1 Slot 2
BIT_CLK
SDATA_OUT
W rite to
0x56
Data
MLNK
SDATA_IN
Don't care
Ts2_pdown
Note: BIT_CLK not to scale
Figure 7. AC-Link Low Power Mode Timing Diagram
Table 13. ATE Test Mode
(VD = 3.0 to 3.6 V, VA = Charge Pump, TA = 25°C, CL = 50 pF)
Parameter1,2
Symbol
Min
Typ
Max
Unit
Setup to rising edge of RESET (also
Tsetup2rst
15.0
—
—
ns
applies to SYNC)
Rising edge of RESET to Hi-Z delay Toff —
— 25.0 ns
Notes:
1. All AC link signals are normally low through the trailing edge of RESET. Bringing SDATA_OUT high for the trailing edge
of RESET causes AC’97 AC-link outputs to go high impedance, which is suitable for ATE in circuit testing.
2. When the test mode has been entered, AC’97 must be issued another RESET with all AC-link signals low to return to
the normal operating mode.
RESET
SDATA_OUT
SDATA_IN, BIT_CLK
T off
T setup2rst
H i-Z
Figure 8. ATE Test Mode Timing Diagram
Rev. 2.01
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI3014.PDF ] | |
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