PDF SI3018 Data sheet ( Hoja de datos )

Número de pieza	SI3018
Descripción	GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT
Fabricantes	Silicon Laboratories
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No Preview Available ! Si3056 Si3018/19/10 GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT Features Complete DAA includes the following:  Programmable line interface  AC termination  DC termination     Ring detect threshold  Ringer impedance    80 dB dynamic range TX/RX paths  Integrated codec and 2- to 4-wire  hybrid   Integrated ring detector   Type I and II caller ID support   Line voltage monitor   Loop current monitor  Polarity reversal detection   Programmable digital gain   Clock generation Pulse dialing support Overload detection 3.3 V power supply Direct interface to DSPs Serial interface control for up to eight devices >5000 V isolation Proprietary isolation technology Parallel handset detection +3.2 dBm TX/RX level mode Programmable digital hybrid for near- end echo reduction Low-profile SOIC packages Lead-free/RoHS-compliant packages available Applications  V.92 modems  Set-top boxes  Voice mail systems  Fax machines  Multi-function printers  Internet appliances  Personal digital assistants Description The Si3056 is an integrated direct access arrangement (DAA) with a programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages, it eliminates the need for an analog front end (AFE), isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3056 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements. The Si3056 interfaces directly to standard modem DSPs. Functional Block Diagram MCLK SCLK FSYNC SDI SDO FC/RGDT RGDT/FSD/M1 OFHK M0 RESET AOUT/INT Si3056 Digital Interface Control Interface Isolation Interface Si3018/19/10 Isolation Interface Hybrid and dc Termination Ring Detect Off-Hook RX IB SC DCT VREG VREG2 DCT2 DCT3 RNG1 RNG2 QB QE QE2 Ordering Information See page 87. Pin Assignments Si3056 MCLK FSYNC SCLK VD SDO SDI FC/RGDT RESET 1 2 3 4 5 6 7 8 16 OFHK 15 RGDT/FSD/M1 14 M0 13 VA 12 GND 11 AOUT/INT 10 C1A 9 C2A Si3018/19/10 QE DCT RX IB C1B C2B VREG RNG1 1 2 3 4 5 6 7 8 16 DCT2 15 IGND 14 DCT3 13 QB 12 QE2 11 SC 10 VREG2 9 RNG2 US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending Rev. 1.06 8/16 Copyright © 2016 by Silicon Laboratories Si3056 1 page Si3056 Si3018/19/10 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter1 Symbol Test Condition Min2 Typ Max2 Unit Ambient Temperature Si3056 Supply Voltage, Digital3 TA F and K-Grade 0 25 70 °C VD 3.0 3.3 3.6 V Notes: 1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 3. 3.3 V applies to both the digital and serial interface and the digital signals RGDT/FSD, OFHK, RESET, M0, and M. Rev. 1.06 5 5 Page Si3056 Si3018/19/10 Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 0) (VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF) Parameter Symbol Min Typ Max Unit Cycle time, SCLK tc 244 1/256 Fs — SCLK Duty Cycle tdty — 50 — Delay Time, SCLKto FSYNC td1 — — 20 Delay Time, SCLK to SDO Valid td2 — — 20 Delay Time, SCLKto FSYNC td3 — — 20 Setup Time, SDI Before SCLK  tsu 25 — — Hold Time, SDI After SCLK  th 20 — — Setup Time, FC Before SCLK tsfc 40 — — Hold time, FC After SCLK thfc 40 — — Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. ns % ns ns ns ns ns ns ns SCLK FSYNC (mode 0) FSYNC (mode 1) 16-Bit SDO 16-Bit SDI FC tc td1 VOH VOL td3 td3 td2 D15 D14 tsu th D15 D14 D1 DD00 D1 D0 tsfc thfc Figure 3. Serial Interface Timing Diagram (DCE = 0) Rev. 1.06 11 11 Page

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