PDF MT90221 Data sheet ( Hoja de datos )

Número de pieza	MT90221
Descripción	Quad IMA/UNI PHY Device
Fabricantes	Mitel Networks Corporation
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MT90221 Quad IMA/UNI PHY Device Features • Cost effective, single chip, 4-port ATM IMA and UNI processor • Up to 4 IMA groups over 4 T1/E1 links can be implemented • Supports MIXED mode; links not assigned to an IMA group can be used in UNI mode • Versatile PCM Interface to most popular T1 or E1 framers, reducing development time • Supports Symmetrical and Asymmetrical Operation • Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) clocking modes • Supports T1 ISDN lines • Provides UTOPIA Level 2 MPHY Interface (MT90221 device slaved to ATM device) • Complies with ITU G.804 recommendations for performing cell mapping into T1 and E1 transmission systems • Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process DS5065 ISSUE 4 December 1999 Ordering Information MT90221AL 208 Pin MQFP -40°C to +85°C • Provides Header Error Control (HEC) veriﬁcation and generation, error detection, Filler cell ﬁltering (IMA mode) and Idle/ Unassigned cell ﬁltering (UNI mode) • Provides statistics to support MIB • Connects to popular asychronous SRAM • Provides statistics on the number of HEC errors • 8 bit Microprocessor Interface, compatible with Intel and Motorola • 3.3V operation / 5V tolerant inputs • MQFP-208 pin • JTAG Test support RX External Static RAM Utopia Level 2 BUS Utopia I/F CTRL Utopia FiFo Processor I/F 4 Internal IMA Processors 4 ... Cell .1 Delineator 4 x CD Circuit Transmission 4.... Convergence 1 4 x TC Circuit T1/E1 Framers 2.048 or 1.544 Mb/s P/S T1/E1 Framers P/S T1/E1 Framers 4 Serial PCM Ports Figure 1 - MT90221 Block Diagram with Built-in IMA functions for 4 IMA Groups over up to 4 links 1 1 page Table of Contents MT90221 6.0 Support Blocks............................................................................................................................................. 33 6.1 Counter Block........................................................................................................................................... 33 6.1.1 UTOPIA Input I/F counters............................................................................................................... 33 6.1.2 Transmit PCM I/F Counters ............................................................................................................. 33 6.1.3 Receive PCM I/F Counters .............................................................................................................. 33 6.1.4 Access to the Counters .................................................................................................................... 33 6.2 Interrupt Block .......................................................................................................................................... 34 6.2.1 IRQ Master Status and IRQ Master Enable Registers..................................................................... 34 6.2.2 IRQ Link Status and IRQ Link Enable Registers.............................................................................. 34 6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ Link 0 Enable Registers .......................................... 35 6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers ............................. 36 6.2.4 IRQ IMA Group Overflow Status and Enable Registers................................................................... 36 6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers .............. 36 6.3 Register and Memory Map ....................................................................................................................... 36 6.3.1 Access to the Various Registers ...................................................................................................... 36 6.3.2 Direct Access ................................................................................................................................... 37 6.3.3 Indirect Access................................................................................................................................. 37 6.3.4 Clearing of Status Bits...................................................................................................................... 37 6.3.4.1 Toggle Bit .................................................................................................................................. 37 6.3.5 Test Modes ...................................................................................................................................... 37 7.0 Register Descriptions .................................................................................................................................. 40 7.1 Utopia Register Description...................................................................................................................... 41 7.2 TX Registers Description.......................................................................................................................... 45 7.3 TX ICP Register Description .................................................................................................................... 50 7.4 RX Registers Description ......................................................................................................................... 52 7.5 RX ICP Cell Registers Description ........................................................................................................... 56 7.6 External SRAM Register Description ....................................................................................................... 58 7.7 RX Delay Registers Description ............................................................................................................... 60 7.8 RX Recombiner Registers Description ..................................................................................................... 63 7.9 TX/RX and PLL Control Registers Description......................................................................................... 65 7.10 Counter Registers Description ................................................................................................................ 70 7.11Interrupt Registers Description ................................................................................................................. 72 7.12 Miscellaneous Registers Description ...................................................................................................... 76 8.0 Application Notes......................................................................................................................................... 77 8.1 Connecting the MT90220 to Various T1/E1 Framers ............................................................................... 77 9.0 AC/DC Characteristics................................................................................................................................. 83 iii 5 Page MT90221 VSS REFCK_3 REFCK_2 REFCK_1 REFCK_0 SR_A_18 SR_A_17 SR_A_16 SR_A_15 SR_A_14 VDD VSS SR_A_13 SR_A_12 SR_A_11 SR_A_10 VDD VSS SR_A_9 SR_A_8 SR_A_7 SR_A_6 SR_A_5 VDD VSS SR_A_4 SR_A_3 SR_A_2 SR_A_1 SR_A_0 SR_WE SR_D_7 SR_D_6 SR_D_5 SR_D_4 SR_D_3 VDD VSS SR_D_2 SR_D_1 SR_D_0 SR_CS 1 SR_CS_0 VSS VDD RXSOC RXCLAV VDD RXDATA_7 RXDATA_6 RXDATA_5 VSS 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 158 102 160 100 162 98 164 96 166 94 168 92 170 90 172 88 174 86 176 84 178 82 180 80 182 208 PIN MQFP 78 184 76 186 74 188 72 190 70 192 68 194 66 196 64 198 62 200 60 202 58 204 56 206 54 208 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 VSS TXCKIO_2 VDD TXCKIO_3 VSS DSTO_3 TXSYNCIO_3 NC NC VSS NC VDD NC VSS NC NC NC NC VDD NC VSS NC VDD NC NC VSS VDD TEST2 TEST1 VDD CLK VSS TCK TMS TDI TRST TDO UP_IRQ VDD UP_A_0 UP_A_1 UP_A_2 UP_A_3 UP_A_4 UP_A_5 UP_A_6 UP_A_7 UP_A_8 UP_A_9 UP_A_10 RESET VSS Pin Description Figure 2 - Pin Connections Pin # Name I/O Description 22, 23, 24, 25, 26, 27, 28, 29 21 TxData [7:0] TxSOC ATM Input Port Signals (UTOPIA Transmit Interface) I UTOPIA Transmit Data Bus. Byte-wide data driven from ATM LAYER device to MT90221. Bit 7 is the MSB. All arriving data between the last byte of the previous cell and the ﬁrst byte of the following cell (indicated by the SOC signal) is ignored. I UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM LAYER device when TxData[7:0] contains the ﬁrst valid byte of the cell. After this signal is high, the following 52 bytes should contain valid data. The MT90221 waits for another TxSOC signal after reading a complete cell. 3 11 Page

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