PDF MT9044 Data sheet ( Hoja de datos )

Número de pieza	MT9044
Descripción	T1/E1/OC3 System Synchronizer
Fabricantes	Mitel Networks Corporation
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Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces • Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces • Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals • Provides C1.5, C2, C3, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals • Provides 5 different styles of 8 KHz framing pulses • Holdover frequency accuracy of 0.05 PPM • Holdover indication • Attenuates wander from 1.9Hz • Provides Time Interval Error (TIE) correction • Accepts reference inputs from two independent sources • JTAG Boundary Scan Applications • Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems • ST-BUS clock and frame pulse sources OSCi OSCo TCLR MT9044 T1/E1/OC3 System Synchronizer Advance Information DS5058 ISSUE 3 September 1999 Ordering Information MT9044AP MT9044AL 44 Pin PLCC 44 Pin MQFP -40 to +85 °C Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and MTIE requirements for these speciﬁcations. VDD VSS TCK TDI TMS TRST TDO PRI SEC RSEL LOS1 LOS2 Master Clock IEEE 1149.1a TIE Corrector Circuit Virtual Reference DPLL Reference Select MUX Reference Select Selected Reference TIE Corrector Enable State Select State Select Input Impairment Monitor Automatic/Manual Control State Machine Guard Time Circuit Output Interface Circuit Feedback Frequency Select MUX APLL MS1 MS2 RST HOLDOVER GTo GTi FS1 Figure 1 - Functional Block Diagram FS2 C19o C1.5o C3o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP ACKi ACKo 1 1 page Advance Information MT9044 Functional Description The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 shows the functional block diagram which is described in the following sections. Reference Select MUX Circuit The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables 1, 4 and 5. Frequency Select MUX Circuit The MT9044 operates with one of three possible input reference frequencies (8kHz, 1.544MHz or 2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1. FS2 FS1 Input Frequency 00 Reserved 01 8kHz 10 1.544MHz 11 2.048MHz Table 1 - Input Frequency Selection Time Interval Error (TIE) Corrector Circuit The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the output signals will occur. A phase step at the input of the DPLL will lead to unacceptable phase changes in the output signal. As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch, from one reference to the other, the State Machine ﬁrst changes the mode of the device PRI or SEC from Reference Select Mux Programmable Delay Circuit TCLR Resets Delay Control Circuit Control Signal Delay Value Compare Circuit TIE Corrector Enable from State Machine Feedback Signal from Frequency Select MUX Figure 3 - TIE Corrector Circuit Virtual Reference to DPLL 5 5 Page Advance Information MT9044 Description State Input Controls Freerun Normal (PRI) Normal (SEC) MS2 MS1 RSEL GTi S0 S1 S2 00 00 00 01 01 10 0 0 1 0 1 X 0 1 X X X X S1 - S1 MTIE S1 - S1 MTIE S2 S2 MTIE - / S1H / / S2H S2H - S0 S0 Legend: - No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State Table 4 - Manual Control State Table Holdover (PRI) S1H S1 S1 MTIE S2 MTIE - / S0 Holdover (SEC) S2H S1 MTIE S1 MTIE S2 MTIE / - S0 S0 Freerun (10X) S1 Normal Primary (000) {A} S1A Auto-Holdover Primary (000) S2A Auto-Holdover Secondary (001) {A} S2 Normal Secondary (001) (GTi=0) (GTi=1) S1H Holdover Primary (010) S2H Holdover Secondary (011) NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) Figure 7 - Manual Control State Diagram 11 11 Page

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