PDF MT9075B Data sheet ( Hoja de datos )

Número de pieza	MT9075B
Descripción	E1 Single Chip Transceiver
Fabricantes	Mitel Networks Corporation
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Features • Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package • Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1) • LIU dynamic range of 20 dB • Enhanced performance monitoring and programmable error insertion functions • Low jitter DPLL for clock generation • Operating under synchronized or free run mode • Two-frame receive elastic buffer with controlled slip direction indication • Selectable transmit or receive jitter attenuator • Intel or Motorola non-multiplexed parallel microprocessor interface • CRC-4 updating algorithm for intermediate path points of a message-based data link application • ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling Applications • E1 add/drop multiplexers and channel banks • CO and PBX equipment interfaces • Primary Rate ISDN nodes • Digital Cross-connect Systems (DCS) MT9075B E1 Single Chip Transceiver Preliminary Information ISSUE 1 March 1998 Ordering Information MT9075BP 68Pin PLCC MT9075BL 100 Pin MQFP -40°C to 85°C Description The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line. The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450. DSTi CSTi Tdi Tdo Tms Tclk Trst INT/MOT IRQ D7~D0 AC4 ~AC0 R/W/WR CS DS/RD DSTo CSTo TxDL TxDLCLK TxMF TAIS ST-BUS Interface Transmit Framing, Error and Test Signal Generation Line Driver ST Loop PL Loop Data Link, HDLC0, HDLC1 National Bit Buffer CAS Buffer Jitter Attenuator & Clock Control DG Loop ST-BUS Interface Receive Framing, Performance Monitoring, Alarm Detection, 2 Frame Slip Buffer RxDLCLK RxDL RxMF LOS RxFP/Rx64kCK E2o F0b C4b Figure 1 - Functional Block Diagram TTIP TRING MS/FR M/S OSC1 OSC2 RTIP RRING 1 1 page Preliminary Information MT9075B Pin Description (continued) Pin # PLCC MQFP Name Description 45 33 C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS sections and transmit serial PCM data of the MT9075B. In the free-run (BL/FR=0) or line synchronous mode (BL/FR=1 and BS/LS=0) this signal is an output, while in the system bus synchronous mode (BS/LS=1) this signal is an input clock. 46 34 F0b Frame Pulse (Input/Output). This is the ST-BUS or GCI frame synchronization signal, which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the PCM30 link. In the free-run (BL/FR=0) or loop synchronous mode (BL/FR=1 and BS/ LS=0) this signal is an output, while in the Bus Synchronous mode (BL/FR=1 and BS/ LS=0) this signal is an input. The GCI/ST-BUS selection is made under software control. Page 02H, address 13H, bit 0, GCI/ST=1 selects GCI frame pulse; GCI/ST=0 selects ST- BUS. 47 35 RxFP/ Receive Frame Pulse/Receive CCS Clock (Output). An 8kHz pulse signal, which is Rx64KCK low for one extracted clock period. This signal is synchronized to the receive PCM 30 basic frame boundary. When 64KCCS (page 01H, address 1AH, bit 0) is set to 1, this pin outputs a 64 kHz clock derived by dividing down the extracted 2.048 MHz clock. This clock is used to clock CCS data out of pin CSTo in the CCS mode. 48 36 IC Internal Connection. Must be left open for normal operation. 49 37 VSS Negative Power Supply (Input). Digital ground. 50 38 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%). 51 39 VDDATx Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter (+5V ± 5%). 52 40 TTIP Transmit TIP and RING (Outputs). Differential outputs for the transmit line signal - must 53 41 TRING be transformer coupled (See Figure 4). 54 42 GNDATx Transmit Analog Ground (Input). Analog ground for the LIU transmitter. 55 43 Tdi IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high. 56 44 Tdo IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected. 57 45 Tms IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled high. 58 46 Tclk IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high. 59 47 Trst IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low. 60 48 TAIS Transmit Alarm Indication Signal (Input). An active low on this input causes the MT9075B to transmit an AIS (all ones signal) on TTIP and TRING pins. TAIS should be set to high for normal data transmission. 61 57 LOS Loss of Signal or Synchronization (Output). When high, and LOS/LOF (page 02H address 13H bit 2) is zero, this signal indicates that the receive portion of the MT9075B is either not detecting an incoming signal (bit LLOS on page 03H address 18H is one) or is detecting a loss of basic frame alignment condition (bit SYNC on page 03H address 10H is one). If LOS/LOF=1, a high on this pin indicates a loss of signal condition. 62 58 59 IC Internal Connection. Tie to VSS (Ground) for normal operation. NC No Connection. Leave open for normal operation. 63 60 IC Internal Connection. Tie to VSS (Ground) for normal operation. 5 5 Page Preliminary Information MT9075B Mode Name BS/LS BL/FR JAS JAT/JAR Note SysBusSync1 1 11 1 JA on Tx side; No JA on Rx side SysBusSync2 1 11 0 JA on Rx side; No JA on Tx side SysBusSync3 1 10 x No JA on Tx or Rx side Line Synchronous 0 1x x By default, JA is on the receive side. Controls bits need not be selected. Free-Run x 0 x x In free-run mode JA will be automatically disconnected Table 2 - Selection of Clock Jitter Attenuation Modes Depending on the mode selected, the Jitter Attenuator (JA) can attenuate either transmit clock jitter or receive clock jitter, or be disconnected. Control bits JAS, JAT/JAR (address 18H of page 02H) determine the JA selection under certain modes. Table 2 shows the conﬁguration of related control pins and control bits required to place the MT9075B in the appropriate jitter attenuation mode. Referring to the mode names given in Table 2, the basic operation of the jitter attenuation modes is summarized as follows: clock before it has been dejittered. The transmit data is synchronous to the clean receive clock. • In Free-Run mode the transmit data is synchronized to the internally generated clock. The internal clock is output on pin C4b. The clock signal extracted from the receive data is not dejittered and is output directly on pin E2o. The PCM 30 Interface • In SysBusSync (1-3) modes, pins C4b and F0b are always configured as inputs, while in the Line Synchronous and Free-Run modes C4b and F0b are configured as outputs. • In SysBusSync1 mode, an external clock is applied to C4b. The applied clock is dejittered by the internal PLL before being used to transmit data. The clock extracted (with no jitter attenuation performed) from the receive data can be monitored on pin E2o. • In SysBusSync2 mode, the clock applied to pin C4b is assumed to be jitter-free and is directly used to transmit data. The internal PLL is used to dejitter the extracted receive clock. The dejittered receive clock is output on pin E2o. • In SysBusSync3 mode, no jitter attenuation is applied to either the transmit or receive clocks. The transmit data is synchronized to clock applied to pin C4b. The extracted receive clock is not dejittered and is supplied directly to the E2o output. • In Line Synchronous mode, the clock extracted from the receive data is dejittered using the internal PLL and then output on pin C4b. Pin E2o provides the extracted receive PCM 30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which results in an aggregate bit rate of 256 bits x 8000/sec = 2.048 Mbits/sec. The actual bit rate is 2.048 Mbits/sec +/-50 ppm encoded in HDB3 format. The HDB3 control bit (page 01H, address 15H, bit 5) selects either HDB3 encoding or alternate mark inversion (AMI) encoding. Basic frames are divided into 32 time slots numbered 0 to 31, see Figure 31. Each time slot is 8 bits in length and is transmitted most signiﬁcant bit ﬁrst (numbered bit 1). This results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec. It should be noted that the Mitel ST-BUS also has 32 channels numbered 0 to 31, but the most signiﬁcant bit of an eight bit channel is numbered bit 7 (see Mitel Application Note MSAN-126). Therefore, ST- BUS bit 7 is synonymous with PCM 30 bit 1; bit 6 with bit 2: and so on (Figure 31). PCM 30 time slot 0 is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication of maintenance information. In most conﬁgurations time slot 16 is reserved for either Channel Associated Signalling (CAS or ABCD bit signalling) or Common Channel Signalling (CCS). The remaining 30 time slots are called channels and carry either PCM encoded voice signals or digital 11 11 Page

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