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MTV003N Schematic ( PDF Datasheet ) - Myson

Teilenummer MTV003N
Beschreibung Microprocessor Compatible Monitor Controller
Hersteller Myson
Logo Myson Logo 




Gesamt 13 Seiten
MTV003N Datasheet, Funktion
MYSON
TECHNOLOGY
MTV003N
(MTV003)
Microprocessor Compatible Monitor Controller
FEATURES
Synchronous signal processing for use in green monitor applications.
Easy command interface for external microprocessor controls.
D/A converters up to 12V output.
Built-in self-test pattern generator.
On-chip clock oscillator allows external TTL level clock signal input.
GENERAL DESCRIPTION
MTV003 is intended for use in digital-controlled, power-conscious (Green) monitor applications. It integrates 4
major function blocks traditionally implemented in discrete parts and provides an easy interface for
microprocessor controls. The functional blocks included in MTV003 are: SYNC processing, D/A converters,
self-test pattern generator and command interface.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV003 Revision 2.3 07/01/1998
1/13






MTV003N Datasheet, Funktion
MYSON
TECHNOLOGY
MTV003N
(MTV003)
Reg4
Reg5
Reg6
Reg7
Reg8
Reg9
Reg10
Reg11
Reg12
Reg13
Reg14
Reg15
Reg16
Reg17
Reg18
I
Reg25
Reg26
Reg27
Reg28
Reg29
Reg30
Reg31
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
I
11001
11010
11011
11100
11101
11110
11111
1 Reserved
1 Reserved
1
HBD0 HBD1 HBD2 HBD3 HBD4 HBD5 HBD6
HBD7
1 HBW0 HBW1 HBW2 HBW3 HBW4 HBW5 HBW6 HBW7
1 Reserved
1 VBW0 VBW1 VBW2 VBW3 VBW4 VBW5 x
VBW7
1 DA0b0 DA0b1 DA0b2 DA0b3 DA0b4 DA0b5 DA0b6 DA0b7
1 DA1b0 DA1b1 DA1b2 DA1b3 DA1b4 DA1b5 DA1b6 DA1b7
1 DA2b0 DA2b1 DA2b2 DA2b3 DA2b4 DA2b5 DA2b6 DA2b7
1 Reserved
1 Reserved
1 Reserved
1 STF RT0 RT1 STbsh Selft x
x
x
1 xxxxxxx
x
Reserved
1 XA0b0 XA0b1 XA0b2 XA0b3 XA0b4 XA0b5 XA0b6 XA0b7
1 XA1b0 XA1b1 XA1b2 XA1b3 XA1b4 XA1b5 XA1b6 XA1b7
1 XA2b0 XA2b1 XA2b2 XA2b3 XA2b4 XA2b5 XA2b6 XA2b7
1 XA3b0 XA3b1 XA3b2 XA3b3 XA3b4 XA3b5 XA3b6 XA3b7
1 XA4b0 XA4b1 XA4b2 XA4b3 XA4b4 XA4b5 XA4b5 XA4b7
1 Reserved
* The above x may represent any data.
- Command Descriptions
Reg0 (write) : Begins the H-Freq count. To read the value in the H-Freq registers, the write command (Reg0)
needs to be issued first.
Reg0 (read)
Reg1 (read)
: The status of polarity, presence and static level for HS and VS.
1. Hpol, Vpol
= 1 -> positive,
= 0 -> negative.
2. HSpre, VSpre, HVpre
= 1 -> present,
= 0 -> not present.
3. Hsl, Vsl
= 1 -> high,
= 0 -> low.
* HVpre represents the status of the composite (H/V) presence in HS. Hsl or Vsl is valid only
when HSpre or VSpre is not present.
: Hfreq Count Finish flags, Hfreq high bit.
1. HCFF
= 1 -> valid,
2. HF10 - HF8
= 3 high bit of Hfreq.
= 0 -> not valid.
Reg1 (write)
: Selects the source of VBLANK and controls the polarity status of Hpol, Vpol
and SYNC output polarity.
1. HVcvs
= 1 -> VBLANK is extracted from HS.
= 0 -> VBLANK is extracted from VS.
2. HBpl = 1 -> negative HBLANK output,
= 0 -> positive HBLANK output.
3. VBpl = 1 -> negative VBLANK output,
= 0 -> positive VBLANK output.
* After power-on, HBpl and VBpl shall be initialized to 0.
4. Hpf1, Hpf0 = 0,0 or 1,1 -> Hpol
= x, by auto detection.
= 0,1
-> force Hpol = 1.
= 1,0
-> force Hpol = 0.
5. Vpf1, Vpf0 = 0,0 or 1,1 -> Vpol
= x, by auto detection.
MTV003 Revision 2.3 07/01/1998
6/13

6 Page









MTV003N pdf, datenblatt
MYSON
TECHNOLOGY
MTV003N
(MTV003)
Figure 6. 4 Self-Test Patterns
12/13
MTV003 Revision 2.3 07/01/1998

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