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PDF MTV003 Data sheet ( Hoja de datos )
| Número de pieza | MTV003 | |
| Descripción | Microprocessor Compatible Monitor Controller | |
| Fabricantes | Myson | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MTV003 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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MYSON
TECHNOLOGY
MTV003N
(MTV003)
Microprocessor Compatible Monitor Controller
FEATURES
• Synchronous signal processing for use in green monitor applications.
• Easy command interface for external microprocessor controls.
• D/A converters up to 12V output.
• Built-in self-test pattern generator.
• On-chip clock oscillator allows external TTL level clock signal input.
GENERAL DESCRIPTION
MTV003 is intended for use in digital-controlled, power-conscious (Green) monitor applications. It integrates 4
major function blocks traditionally implemented in discrete parts and provides an easy interface for
microprocessor controls. The functional blocks included in MTV003 are: SYNC processing, D/A converters,
self-test pattern generator and command interface.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
MTV003 Revision 2.3 07/01/1998
1/13
1 page  
MYSON
TECHNOLOGY
MTV003N
(MTV003)
V-Freq(Hz)
1 20
2 56.25
3 59.94
4 60
5 60.32
6 60.53
7 66.67
8 70.069
9 70.08
10 72
11 72.378
12 72.7
13 87
Output value hexadecimal 9 bits decimal
30D 781
115 277
104 260
104 260
103 259
102 258
0EA 234
0DE 222
0DE 222
0D9 217
0D7 215
0D6 214
0B3 179
Tolerance (%)
0.12804
0.36101
0.38461
0.38461
0.38610
0.38759
0.42735
0.45045
0.45045
0.46082
0.46511
0.46728
0.55865
3.6 Command Interface
The command interface contains 3 pins. Each transfer of command is comprised of 16 DCK clock periods. The
first 8 DCK clocks are for the address and direction of DIO, and the succeeding 8 DCK clocks are for the data.
Each transfer is initiated by setting CMDB Low. The CMDB pin must be pulled High after data transfer is
completed.
- Command Format
B0 - 4 (ADD4 - 0)
B5 (W/RB)
B6 - 7
B8 - 15 (DA0 - 7)
(DA7 - 0)
- Register Allocation
a. Read Transfer
: Address of the registers.
: Transfer direction, 1=write, 0=read.
: Reserved.
: Data input when W/RB=1.
Data output when W/RB=0.
Reg #
Reg0
Reg1
Reg2
Reg3
Reg4
Address Portion
ADD4-0 W/RB
B0 - 4
B5
00000
0
00001
0
00010
0
00011
0
00100
0
B8
Hpol
x
HF7
x
VF7
Data Portion
DA7 - 0
B9 B10 B11 B12 B13 B14 B15
Vpol HSpre VSpre HVpre Hsl
Vsl
x
x
x
x
HCFF HF10 HF9
HF8
HF6 HF5 HF4 HF3 HF2 HF1 HF0
x x x x x VCFF VF8
VF6 VF5 VF4 VF3 VF2 VF1 VF0
Table 4
b. Write Transfer
Reg #
Reg0
Reg1
Reg2
Reg3
Address Portion
ADD4-0 W/RB
B0 - 4
B5
00000
1
00001
1
00010
1
00011
1
B8
x
Vpf0
x
CLK4M
B9
x
Vpf1
x
TEST
B10
x
Hpf0
x
x
5/13
Data Portion
DA0 - 7
B11 B12
xx
Hpf1
VBpl
xx
xx
B13
x
HBpl
x
x
B14
x
HVcvs
x
x
B15
x
x
x
x
MTV003 Revision 2.3 07/01/1998
5 Page 
MYSON
TECHNOLOGY
8.0 TIMING DIAGRAMS
MTV003N
(MTV003)
11/13
MTV003 Revision 2.3 07/01/1998
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MTV003.PDF ] | |
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