PDF STLC3065 Data sheet ( Hoja de datos )

Número de pieza	STLC3065
Descripción	WLL SUBSCRIBER LINE INTERFACE CIRCUIT
Fabricantes	ST Microelectronics
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No Preview Available ! ® STLC3065 WLL SUBSCRIBER LINE INTERFACE CIRCUIT MONOCHIP SLIC OPTIMISED FOR WLL AP- PLICATIONS IMPLEMENT ALL KEY FEATURES OF THE BORSHT FUNCTION SINGLE SUPPLY (5.5 TO 15.8V) BUILT IN DC/DC CONVERTER CONTROL- LER. SOFT BATTERY REVERSAL WITH PRO- GRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR THRESHOLD METERING PULSE GENERATION AND FIL- TER INTEGRATED RINGING INTEGRATED RING TRIP DUAL 2W PORT FOR DATA/VOICE OPERA- TION PARALLEL CONTROL INTERFACE (3.3V LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT FEEDER SURFACE MOUNT PACKAGE BLOCK DIAGRAM TQFP44 ORDERING NUMBERS: STLC3065Q STLC3065QTR INTEGRATED THERMAL PROTECTION -40 TO +85°C OPERATING RANGE DESCRIPTION The STLC3065 is a SLIC device specifically de- signed for WLL (Wireless Local Loop) application. One of the distinctive characteristics of this de- vice is the ability to operate with a single supply voltage (from +5.5V to +15.8V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external D0 D1 D2 P1 P2 DET DET1 DET2 TX RX ZAC1 ZAC RS ZB CKTTX C TTX1 CTTX2 FTTX IN PUT LOGIC AND DECODER Status and functions AC PROC SUPERVISION OUTPUT LOGIC LINE D RIVER LINE SWITCH BGND TIP1 TIP2 R ING1 RING2 TTX PROC REFERENCE Vcc Vss A gnd DC PROC C REV CSVR DC/DC CONV. C LK R SENSE GATE VF VOLT. REG. Vbat CVCC V POS VBAT RTTX CAC ILTF R D IREF RLIM RTH AGND October 1999 1/27 1 page FUNCTIONAL DIAGRAM STLC3065 Tip1 Ring1 Tip2 Ring2 SW4T SW3T SW1T SW1T SW2T SW2R CONTROL INTERFACE SLIC core TX RX SW4R 300µA SW6R SW5R SW3R 300µA DC/DC converter controller The STLC3065 operating modes will be obtained as combination of the SLIC core status and the dual port configuration. The DC/DC converter controller is driving an ex- ternal power MOS transistor (P-Channel) in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHz typ.). From version marked STLC3065 A5, it can be synchronised to an internal clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). The typical value is obtained for a sensing resis- tor equal to 110mΩ that will guarantee an aver- age current consumption from Vpos < 700mA. In on-hook condition the self generated battery voltage is set to a predefined value. This value can be adjusted via one external resis- tor (RF1) and it is typical -50V. When RING mode is selected this value is increased up to -70V typ. Once the line goes in off-hook condition the DC/DC converter automatically adjust the gener- ated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) opti- mising in this way the power dissipation. The Dual Port allows to connect the SLIC core to one of the two possible 2W ports (TIP1/RING1, TIP2/RING2). Dual port concept One switches array integrated in STLC3065 al- lows to connect the TIP and RING output of the SLIC core to one of the two 2W ports (TIP1/RING1 or TIP2/RING2). For special condi- tions it is also possible to connect both ports to the SLIC core.The structure of the switches array is shown in fig.1 and it is controlled via the two logic inputs P1 and P2. Depending on the switches configurations each 2W port (TIP1/RING1 or TIP2/RING2) can be set in four possible conditions: Open Connected to BGND and Battery via two inte- grated 1.5KΩ resistors. Connected to the SLIC core Connected to an internal 300µA (min.) current source. Depending on the SLIC core operating modes (defined by D0,D1 and D2) only a subset of these conditions can be programmed. 5/27 5 Page STLC3065 Depending on the P1,P2 control bits the ring waveform can be applied to both 2W ports (TIP1/RING1 and TIP2/RING2) or to one of the two (see also table2). The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC off- set superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is opti- mised for operation on short loop applications and may not operate properly in presence of long loop applications (>500Ω). Once ring trip is detected, the DET output is acti- vated (logic level low), at this point the card con- troller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3065 in the proper operating mode (Normally ACTIVE). RING LEVEL IN PRESENCE OF MORE TELE- PHONE IN PARALLEL. As already mentioned above the maximum cur- rent that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be re- duced. In the typical application with RSENSE = 110mW the peak current from Vpos is limited to about 900mA, which correspond to an average current of 700mA max. In this condition the STLC3065 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard). In order to drive up to 5REN (1REN= 6930Ω + 8mF, US standard) it is necessary to modify the external components as follows: CREV = 15nF RD = 2.2 KΩ Power On Requirements In order to avoid damage to the device when Vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0V) until Vpos is > 5.5V. In case this power up sequence cannot be guar- anteed, it’s recommended to connect a shottky di- ode (BAT46 or equivalent) between VBAT and BGND (see figure 7). Figure 7. Shottky diode connection BGND STLC3065 VBAT BAT46 Layout Recommendation A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground con- nection and in this case the star configuration al- lows surely to avoid possible problems (see Appli- cation Diagram Fig. 8). The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point PGND. This point should show a resis- tance as low as possible, that means it should be a ground plane. Noise sources can be identified in not enough good grounds, not enough low impedance sup- plies and parasitic coupling between PCB tracks and high impedance pins of the device. In particular, to avoid noise problems, layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3065 using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch fre- quency on VPOS. 11/27 11 Page

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