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PDF OV6130 Data sheet ( Hoja de datos )
| Número de pieza | OV6130 | |
| Descripción | (OV6130 / OV6630) SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OV6130 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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Advanced Information
Preliminary
OV6630/OV6130
OV6630 SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA
OV6130 SINGLE-CHIP CMOS CIF B&W DIGITAL CAMERA
Features
101,376 pixels, 1/4” lens, CIF/QCIF format
Progressive scan read out
Data format - YCrCb 4:2:2, GRB 4:2:2, RGB Raw Data
8/16 bit video data: ITU-601, ITU-656, ZV port
Wide dynamic range, anti-blooming, zero smearing
Electronic exposure/gain/white balance control
Image enhancement - brightness, contrast, gamma,
saturation, sharpness, window, etc.
Internal/external synchronization
General Description
The OV6630 (color) and OV6130 (black and white) CMOS Im-
age sensors are single-chip video/imaging camera devices
designed to provide a high level of functionality in a single,
small-footprint package. Both devices incorporate a 352 x 288
image array capable of operating up to 60 frames per second
image capture. Proprietary sensor technology utilizes advanced
algorithms to cancel Fixed Pattern Noise (FPN), eliminate
Frame exposure/line exposure option
3.3-Volt operation, low power dissipation
- < 20 mA active power
- < 10 µA in power-save mode
Gamma correction (0.45/0.55/1.00)
I2C programmable (400 kb/s):
- Color saturation, brightness, contrast,
exposure time, gain
white
balance,
smearing, and drastically reduce blooming. All needed camera
functions including exposure control, gamma, gain, white
balance, color matrix, windowing, and more, are programmable
through an I2C interface. Both devices can be programmed to
provide image output in 4-bit, 8-bit or 16-bit digital formats.
Applications include: Video Conferencing, Video Phone, Video
Mail, Still Image, and PC Multimedia.
AGND
AVDD
PWDN
VRCAP1
VcCHG
IICB
VTO
ADVDD
ADGND
VSYNC/CSYS
FODD/CLK
HREF/VSFRAM
7
8
9
10
11
12
13
14
15
16
17
18
OV6630/
OV6130
42 CHSYNC/BW
41 V0/CBAR
40 Y1
39 Y2/G2X
38 Y3/RGB
37 Y4/CS1
36 Y5/SHARP
35 Y6/CS2
34 Y7/CS0
33 PCLK/PWDB
32 DOVDD
31 DOGND
Array Element(CIF)
(QCIF)
Pixel Size
Image Area
Max Frames/Sec
Electronics
Exposure
Scan Mode
Gamma Correction
Min. Illumination
(3000K)
S/N Ration
FPN
Dark Current
Dynamic Range
Power Supply
Power
Requirements
Package
356x292
(176x144)
9µm x 8.2µm
3.1mm x 2.5mm
Up to 60 FPS
Up to 500:1 (for selected
FPS)
Progressive
0.45/0.55/1.0
OV6630 - < 3lux @ f1.2
OV6130 - < 0.5lux @ f1.2
> 48 dB
(AGC off, Gamma=1)
< 0.03% VPP
< 0.2nA/cm2
> 72 dB
2.7−3.6VDC
5VDC/3.3VDC (DIO)
< 20mA active
< 10µA Standby
48 pin LCC
Figure 1. OV6630/OV6130 Pin Assignments
Note: Outputs UV0-UV7 are not available on the OV6130. The inputs associated
with these respective pins are still functional.
OmniVision Technologies, Inc. 930 Thompson Place Sunnyvale, CA 94086 U.S.A.
Tel: (408) 733-3030 Fax: (408) 733-3061
e-mail: [email protected]
Website: http://www.ovt.com
Version 1.0, March 4, 2000
1 page  
VSYNC
HREF
PCLK
Y[7:0]/UV[7:0]
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
t8 t8
Even Field 1 (FODD=0)
Odd Field 1 (FODD=1)
t6
t4
t1
t3
t2
t5
12
Valid Data
Horizontal Timing
t7
351 352
VSYNC
Y[7:0]/UV[7:0]
TVS 1 Line
TVE
TLINE
Vertical Timing
Notes:
1.
2.
Figure 3. Zoom Video Port Timing
Zoom Video Port format output signal includes:
VSYNC: Vertical sync pulse.
HREF: Horizontal valid data output window.
PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom V Port. Default frequency is 8.86MHz when use
17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data.
Y[7:0]: 8 Bit luminance data bus.
UV[7:0]: 8 Bit chrominance data bus.
All timing parameters are provided in Table 13. Zoom Video Port AC Parameters.
1.2.5 QCIF Format
A QCIF mode is available for applications where higher resolution
image capture is not required. Only half of the pixel rate is required
when programmed in this mode. Default resolution is 176 x 144
pixels and can be programmed for other resolutions. Refer to Table 7.
QCIF Digital Output Format (YUV beginning of line) and Table 8.
QCIF Digital Output Format (RGB raw data beginning of line) for
further information.
1.2.6 Video Output
The video output port of the OV6630/OV6130 image sensors
provides a number of output format/standard options to suit many
different application requirements. Table 2. Digital Output Format,
below, indicates the output formats available. These formats are user
programmable through the I2C interface (See I2C Bus Protocol
Format).
March 4, 2000
Version 1.0
5
5 Page 
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
Default mode:
- 1st HREF Y channel output unstable data, UV output B11 G12 B13 G14 ···
- 2nd HREF Y channel output G21 R22 G23 R24 ···, UV output B11 G12 B13 G14 ···
- 3rd HREF Y channel output G21 R22 G23 R24 ···, UV output B31 G23 B33 G34 ···
- Every line of data is output twice.
YG mode:
- 1st HREF Y and UV output unstable data.
- 2nd HREF Y channel output G21 G12 G23 G14 ···, UV output B11 R22 B13 R24 ···
- 3rd HREF Y is G21 G32 G23 G34 ···, UV channel is B31 R22 B33 R24 ···
- Every line data output twice.
One line mode:
- 1st HREF Y channel output B11 G12 B13 G14 ···
- 2nd HREF Y channel output G21 R22 G23 R24 ···
- UV channel tri-state.
2. 8-bit Format (Total 292 HREFs)
- 1st HREF Y channel output unstable data.
- 2nd HREF Y channel output B11 G21 R22 G12 ···
- 3rd HREF Y channel output B31 G21 R22 G32 ···
- PCLK timing is doubled and PCLK rising edge latch data bus. UV channel tri-state. Every line data output twice.
3. 4-bit Nibble Mode Output Format
- Uses higher 4 bits of Y port (Y[7:4]) as output port.
- Supports YCrCb/RGB data, ITU-601/ITU-656 timing, Color/B&W.
- Output sequence: High order 4 bits followed by lower order 4 bits
Y0H Y0L Y1H Y1L ···
U0H U0L V0H V0L ···
For B/W or one-line RGB raw data, the output data clock speed is doubled. For color YUV, output clock is four times that of the 16-bit
output data. In color mode, sensor must be set to 8-bit mode, and the nibble timing, clock divided by 2.
Output sequence: U0H U0L Y0H Y0L V0H V0L Y1H Y1L ···
1.2.7 Slave Mode Operation
The OV6630/OV6130 can be programmed to operate in slave mode
(COMI[6] = 1, default is master mode). HSYNC and VSYNC output
signals are provided.
When used as a slave device, the external master must provide the
following clocks to OV6630/OV6130 imager:
1. System clock CLK to XCLK1 pin
2. Horizontal sync, HSYNC, to CHSYNC pin, positive assertion
3. Vertical frame sync, VSYNC, to VSYNC pin, positive assertion
In slave mode, the OV6630/OV6130 tri-states CHSYNC (pin 42) and
VSYNC (pin 16) output pins, and used as input pins. To synchronize
multiple devices, OV6630/OV6130 uses external system clock, CLK,
to synchronize external horizontal sync, HSYNC, which is then used
to synchronize external vertical frame sync, VSYNC. See Figure 6.
Slave Mode External Sync Timing for timing considerations.
1.2.8 Frame Exposure Mode
OV6630/OV6130 supports frame. FREX (pin 4) is asserted by an
external master device to set exposure time. The pixel array is quickly
pre-charged when FREX is set to “1”. OV6630/OV6130 captures the
image in the time period when FREX remains high. The video data
stream is delivered to output port in a line-by-line manner after FREX
switches to “0”.
It should be noted that FREX must remain high long enough to ensure
the entire image array has been pre-charged.
When data is being output from OV6630/OV6130, care must be taken
so as not to expose the image array to light. This may affect the
integrity of the image data captured. A mechanical shutter synchro-
nized with the frame exposure rate can be used to minimize this
situation. The timing of frame exposure is shown in Figure 7. Frame
Exposure Timing below.
1.2.9 Reset
OV6630/OV6130 includes a RESET pin (pin 2) that forces a
complete hardware reset when it is pulled high (VCC).
OV6630/OV6130 clears all registers and resets to their default values
when a hardware reset occurs. Reset can also be initiated through the
I2C interface.
1.2.10 Power Down Mode
Two methods are available to place OV6630/OV6130 into power-
down mode: hardware power down and I2C software power down.
To initiate hardware power down, the PWDN pin (pin 9) must be tied
to high (+3.3VDC). When this occurs, OV6630/OV6130 internal
device clock is halted and all internal counters are reset. The current
draw is less than 10µA in this standby mode.
March 4, 2000
Version 1.0
11
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet OV6130.PDF ] | |
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