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T89C5115 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer T89C5115
Beschreibung Low Pin Count 8-bit Microcontroller
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
T89C5115 Datasheet, Funktion
Features
80C51 Core Architecture
256 Bytes of On-chip RAM
256 Bytes of On-chip XRAM
16K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
– Erase/Write Cycle: 100K
2K Bytes of On-chip Flash for Bootloader
2K Bytes of On-chip EEPROM
– Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
Three or Four Ports: 16 or 20 Digital I/O Lines
Two-channel 16-bit PCA
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable bits)
A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
Power-saving Modes
– Idle Mode
– Power-down Mode
Power Supply: 3 Volts to 5.5 Volts
Temperature Range: Industrial (-40° to +85°C)
Packages: SOIC28, SOIC24, PLCC28, VQFP32
Low Pin Count
8-bit
Microcontroller
with A/D
Converter and
16 KBytes Flash
Memory
T89C5115
AT89C5115
Rev. 4128G–8051–02/08






T89C5115 Datasheet, Funktion
Pin Name
P3.0:7
P4.0:1
RESET
XTAL1
XTAL2
Type
I/O
I/O
I/O
I
O
Description
Port 3:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled
high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that
are being pulled low externally will be a source of current (IIL, See section ’Electrical Characteristic’)
because of the internal pull-ups.
The output latch corresponding to a secondary function must be programmed to one for that function to
operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:
P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
P3.2/INT0: External interrupt 0 input/timer 0 gate control input
P3.3/INT1: External interrupt 1 input/timer 1 gate control input
P3.4/T0: Timer 0 counter input
P3.5/T1: Timer 1 counter input
P3.6: Regular I/O port pin
P3.7: Regular I/O port pin
Port 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled
high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being
pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up
transistor.
P4.0:
P4.1:
It can drive CMOS inputs without external pull-ups.
Reset:
A high level on this pin during two machine cycles while the oscillator is running resets the device. An
internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.
XTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the
device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To
operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
XTAL2:
Output from the inverting oscillator amplifier.
6 AT89C5115
4128G–8051–02/08

6 Page









T89C5115 pdf, datenblatt
Table 6. PCA SFRs (Continued)
Mnemonic Add Name
CCAP0L
CCAP1L
PCA Compare
EAh Capture Module 0 L
EBh PCA Compare
Capture Module 1 L
76543210
CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0
CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0
Table 7. Interrupt SFRs
Mnemonic Add Name
IEN0
A8h
Interrupt Enable
Control 0
IEN1
E8h
Interrupt Enable
Control 1
IPL0
B8h
Interrupt Priority
Control Low 0
IPH0
B7h
Interrupt Priority
Control High 0
IPL1
F8h
Interrupt Priority
Control Low 1
IPH1
F7h
Interrupt Priority
Control High1
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
EADC
PPC
PT2
PS
PT1 PX1 PT0 PX0
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
PADCL
PADCH
Table 8. ADC SFRs
Mnemonic Add Name
ADCON
F3h ADC Control
ADCF
F6h ADC Configuration
ADCLK
F2h ADC Clock
ADDH
F5h ADC Data High byte
ADDL
F4h ADC Data Low byte
7
CH7
ADAT9
6
PSIDLE
CH6
ADAT8
5
ADEN
CH5
ADAT7
4
ADEOC
CH4
PRS4
ADAT6
3
ADSST
CH3
PRS3
ADAT5
2
SCH2
CH2
PRS2
ADAT4
1
SCH1
CH1
PRS1
ADAT3
ADAT1
0
SCH0
CH0
PRS0
ADAT2
ADAT0
Table 9. Other SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR1
A2h Auxiliary Register 1
CKCON
8Fh Clock Control
FCON
D1h Flash Control
EECON
D2h EEPROM Contol
7
SMOD1
FPL3
EEPL3
6
SMOD0
WDX2
FPL2
EEPL2
5
ENBOOT
PCAX2
FPL1
EEPL1
4
POF
SIX2
FPL0
EEPL0
3
GF1
GF3
T2X2
FPS
2
GF0
0
T1X2
FMOD1
1
PD
T0X2
FMOD0
EEE
0
IDL
DPS
X2
FBUSY
EEBUSY
12 AT89C5115
4128G–8051–02/08

12 Page





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