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PDF T89C51RB2 Data sheet ( Hoja de datos )
| Número de pieza | T89C51RB2 | |
| Descripción | (T89C51RB2/RC2) 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C52 Compatible
– 8051 Pin and Instruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit timer/counters
– 256 Bytes Scratch Pad RAM
– 10 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
• Variable Length MOVX for slow RAM/Peripherals
• ISP (In-System Programming) using Standard VCC Power Supply
• Boot ROM Contains Low Level FLASH Programming Routines and a Default Serial
Loader
• High-Speed Architecture
– 40 MHz in Standard Mode
– 20 MHz in X2 Mode (6 clocks/machine cycle)
• 16K/32K Bytes on-chip FLASH Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 10k Write Cycles
• On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
• Keyboard Interrupt Interface on port P1
• SPI Interface (Master / Slave Mode)
• 8-bit Clock Prescaler
• Improved X2 Mode with Independent Selection for CPU and each Peripheral
• Programmable Counter Array 5 Channels with:
– High Speed Output
– Compare / Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
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• Asynchronous Port Reset
• Full Duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (Inhibit ALE)
• Hardware Watchdog Timer (One-time enabled with Reset-Out)
• Power Control Modes:
– Idle Mode
– Power-down mode
– Power-off Flag
• Power supply: 4.5 to 5.5V or 2.7 to 3.6V
• Temperature ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
• Packages: PDIL40, PLCC44, VQFP44
8-bit
Microcontroller
with 16K/
32K byte Flash
T89C51RB2
T89C51RC2
Preliminary
Description
T89C51RB2/RC2 is a high-performance FLASH version of the 80C51 8-bit microcon-
trollers. It contains a 16K or 32K byte Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
The T89C51RB2/RC2 retains all features of the 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the T89C51RB2/RC2 has a Programmable Counter Array, an XRAM of
1024 bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface,
Rev. 4105D–8051–10/06
1
1 page  
Pin Configurations
Figure 2. Pin Configurations
P1.0/T2
P1.1/T2EX/SS
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
PDIL40 30 ALE/PROG
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
T89C51RB2/RC2
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12
PLCC44
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 VQFP44 1.4 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4105D–8051–10/06
5
5 Page 
T89C51RB2/RC2
Enhanced Features
X2 Feature
Description
In comparison to the original 80C52, the T89C51RB2/RC2 implements some new fea-
tures, which are:
• the X2 option
• the Dual Data Pointer
• the extended RAM
• the Programmable Counter Array (PCA)
• the Hardware Watchdog
• the SPI interface
• the 4-level interrupt priority system
• the power-off flag
• the ONCE mode
• the ALE disabling
• some enhanced features are also located in the UART and the timer 2
The T89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid glitches when switching from X2 to STD mode. Figure 5 shows
the switching mode waveforms.
Figure 4. Clock Generation Diagram
XTAL1
FXTAL
CKRL
XTAL1:2
FOSC
2 0 8 bit Prescaler
1
FCLK CPU
FCLK PERIPH
X2
CKCON0
4105D–8051–10/06
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet T89C51RB2.PDF ] | |
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