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T89C51CC01 Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer T89C51CC01
Beschreibung Enhanced 8-Bit Microcontroller
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 30 Seiten
T89C51CC01 Datasheet, Funktion
Features
80C51 Core Architecture
256 Bytes of On-chip RAM
1K Bytes of On-chip XRAM
32K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Erase/Write Cycle: 100K
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
Erase/Write Cycle: 100K
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
Five Ports: 32 + 2 Digital I/O Lines
Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
Double Data Pointer
21-bit Watchdog Timer (7 Programmable Bits)
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller:
– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:
Each Message Object Programmable on Transmission or Reception
Individual Tag and Mask Filters up to 29-bit Identifier/Channel
8-byte Cyclic Data Register (FIFO)/Message Object
16-bit Status and Control Register/Message Object
16-bit Time-Stamping Register/Message Object
CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
Access to Message Object Control and Data Registers Via SFR
Programmable Reception Buffer Length Up To 15 Message Objects
Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
Priority Management for Transmission
Message Object Overrun Interrupt
– Supports:
Time Triggered Communication
Autobaud and Listening Mode
Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
On-chip Emulation Logic (Enhanced Hook System)
Power Saving Modes:
– Idle Mode
– Power-down Mode
1. At BRP = 1 sampling point will be fixed.
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash Memory
T89C51CC01
AT89C51CC01
Rev. 4129N–CAN–03/08
1






T89C51CC01 Datasheet, Funktion
Table 1. Read-Modify-Write Instructions
Instruction
Description
Example
ANL
logical AND
ANL P1, A
ORL
logical OR
ORL P2, A
XRL
logical EX-OR
XRL P3, A
JBC jump if bit = 1 and clear bit
JBC P1.1, LABEL
CPL
complement bit
CPL P3.0
INC
DEC
increment
decrement
INC P2
DEC P2
DJNZ
decrement and jump if not zero
DJNZ P3, LABEL
MOV Px.y, C move carry bit to bit y of Port x
MOV P1.5, C
CLR Px.y
clear bit y of Port x
CLR P2.4
SET Px.y
set bit y of Port x
SET P3.3
It is not obvious the last three instructions in this list are Read-Modify-Write instructions.
These instructions read the port (all 8 bits), modify the specifically addressed bit and
write the new byte back to the latch. These Read-Modify-Write instructions are directed
to the latch rather than the pin in order to avoid possible misinterpretation of voltage
(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of
an external bipolar transistor can not rise above the transistor’s base-emitter junction
voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU
to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather
than the pins returns the correct logic-one value.
Quasi-Bidirectional Port
Operation
Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as
"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as
logic one and sources current in response to an external logic zero condition. Port 0 is a
"true bidirectional" pin. The pins float when configured as input. Resets write logic one to
all Port latches. If logical zero is subsequently written to a Port latch, it can be returned
to input conditions by a logical one written to the latch.
Note:
Port latch values change near the end of Read-Modify-Write instruction cycles. Output
buffers (and therefore the pin state) update early in the instruction after Read-Modify-
Write instruction cycle.
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-
up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This
extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock
periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-
ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses
logical zero and off when the gate senses logical one. pFET #1 is turned on for two
oscillator periods immediately after a zero-to-one transition in the Port latch. A logical
one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched
on whenever the associated nFET is switched off. This is traditional CMOS switch con-
vention. Current strengths are 1/10 that of pFET #3.
6 A/T89C51CC01
4129N–CAN–03/08

6 Page









T89C51CC01 pdf, datenblatt
Table 9. CAN SFRs (Continued)
Mnemonic Add Name
7
CANIDT1
BCh
CAN Identifier Tag
byte 1(Part A)
CAN Identifier Tag
byte 1(PartB)
IDT10
IDT28
CANIDT2
BDh
CAN Identifier Tag
byte 2 (PartA)
CAN Identifier Tag
byte 2 (PartB)
IDT2
IDT20
CANIDT3
BEh
CAN Identifier Tag
byte 3(PartA)
CAN Identifier Tag
byte 3(PartB)
IDT12
CANIDT4
CAN Identifier Tag
byte 4(PartA)
BFh
CAN Identifier Tag
byte 4(PartB)
IDT4
CANIDM1
CAN Identifier
Mask byte
1(PartA)
C4h
CAN Identifier
Mask byte
1(PartB)
IDMSK10
IDMSK28
CANIDM2
CAN Identifier
Mask byte
2(PartA)
C5h
CAN Identifier
Mask byte
2(PartB)
IDMSK2
IDMSK20
CANIDM3
CAN Identifier
Mask byte
3(PartA)
C6h
CAN Identifier
Mask byte
3(PartB)
IDMSK12
CANIDM4
CAN Identifier
Mask byte
4(PartA)
C7h
CAN Identifier
Mask byte
4(PartB)
IDMSK4
6
IDT9
IDT27
IDT1
IDT19
IDT11
IDT3
IDMSK9
IDMSK27
IDMSK1
IDMSK19
IDMSK11
IDMSK3
5
IDT8
IDT26
IDT0
IDT18
IDT10
IDT2
IDMSK8
IDMSK26
IDMSK0
IDMSK18
IDMSK10
IDMSK2
4
IDT7
IDT25
IDT17
IDT9
IDT1
IDMSK7
IDMSK25
IDMSK17
IDMSK9
IDMSK1
3
IDT6
IDT24
IDT16
IDT8
IDT0
IDMSK6
IDMSK24
IDMSK16
IDMSK8
IDMSK0
2
IDT5
IDT23
IDT15
IDT7
RTRTAG
IDMSK5
IDMSK23
IDMSK15
IDMSK7
RTRMSK
1
IDT4
IDT22
IDT14
IDT6
RB1TAG
IDMSK4
IDMSK22
IDMSK14
IDMSK6
0
IDT3
IDT21
IDT13
IDT5
RB0TAG
IDMSK3
IDMSK21
IDMSK13
IDMSK5
IDEMSK
Table 10. Other SFRs
Mnemonic Add Name
PCON
87h Power Control
AUXR
8Eh Auxiliary Register 0
AUXR1
A2h Auxiliary Register 1
CKCON 8Fh Clock Control
7
SMOD1
CANX2
6
SMOD0
WDX2
5
M0
ENBOOT
PCAX2
4
POF
SIX2
3
GF1
XRS1
GF3
T2X2
2
GF0
XRS2
0
T1X2
1
PD
EXTRAM
T0X2
0
IDL
A0
DPS
X2
12 A/T89C51CC01
4129N–CAN–03/08

12 Page





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