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HPC16064 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer HPC16064
Beschreibung (HPC16064 - HPC46064 / HPC16004 - HPC46004) High-Performance microController
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 37 Seiten
HPC16064 Datasheet, Funktion
May 1992
HPC16064 26064 36064 46064 16004 26004
36004 46004 High-Performance microController
General Description
The HPC46064 and HPC46004 are members of the HPCTM
family of High Performance microControllers Each member
of the family has the same core CPU with a unique memory
and I O configuration to suit specific applications The
HPC46064 has 16k bytes of on-chip ROM The HPC46004
has no on-chip ROM and is intended for use with external
memory Each part is fabricated in National’s advanced
microCMOS technology This process combined with an ad-
vanced architecture provides fast flexible I O control effi-
cient data manipulation and high speed computation
The HPC devices are complete microcomputers on a single
chip All system timing internal logic ROM RAM and I O
are provided on the chip to produce a cost effective solution
for high performance applications On-chip functions such
as UART up to eight 16-bit timers with 4 input capture regis-
ters vectored interrupts WATCHDOGTM logic and MICRO-
WIRE PLUSTM provide a high level of system integration
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips The term ‘‘HPC46064’’ is used throughout this data-
sheet to refer to the HPC46064 and HPC46004 devices un-
less otherwise specified
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings The HPC is available in 68-pin
PLCC LDCC PGA and 80-pin PQFP package
Features
Y HPC family core features
16-bit architecture both byte and word
16-bit data bus ALU and registers
64k bytes of external direct memory addressing
FAST 200 ns for fastest instruction when using
20 0 MHz clock 134 ns at 30 0 MHz
High code efficiency most instructions are single
byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters with 4 synchronous out-
puts and WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS very low power with two power save modes
IDLE and HALT
Y UART full duplex programmable baud rate
Y Four additional 16-bit timer counters with pulse width
modulated outputs
Y Four input capture registers
Y 52 general purpose I O lines (memory mapped)
Y 16k bytes of ROM 512 bytes of RAM on-chip
Y ROMless version available (HPC46004)
Y Commercial (0 C to a70 C) industrial (b40 C to
a85 C) automotive (b40 C to a105 C) and military
(b55 C to a125 C) temperature ranges
Block Diagram (HPC46064 with 16k ROM shown)
Series 32000 and TRI-STATE are registered trademarks of National Semiconductor Corporation
MOLETM HPCTM COPSTM microcontrollers WATCHDOGTM and MICROWIRE PLUSTM are trademarks of National Semiconductor Corporation
IBM and PC-AT are registered trademarks of International Business Machines Corporation
Sun is a registered trademark of Sun Microsystems
SunOSTM is a trademark of Sun Microsystems
C1995 National Semiconductor Corporation TL DD11372
TL DD 11372 – 1
RRD-B30M105 Printed in U S A






HPC16064 Datasheet, Funktion
30 MHz (Continued)
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5 ) VCC e 5V g10% unless otherwise specified TA e 0 C to a70 C for
HPC46064 46004 b40 C to a85 C for HPC36064 36004 b40 C to a105 C for HPC26064 26004 b55 C to a125 C for
HPC16064 16004
Symbol and Formula
Parameter
Min Max Units
Notes
tDC1ALER
Delay from CKI Rising Edge to
ALE Rising Edge
0 35 ns (Notes 1 2)
tDC1ALEF
Delay from CKI Rising Edge to
ALE Falling Edge
0 35 ns (Notes 1 2)
tDC2ALER e tC a 20
Delay from CK2 Rising Edge to
ALE Rising Edge
37 ns
(Note 2)
tDC2ALEF e tC a 20
Delay from CK2 Falling Edge to
ALE Falling Edge
37 ns
(Note 2)
tLL e
tST e
tC b 9
tC b 7
ALE Pulse Width
Setup of Address Valid before
ALE Falling Edge
24 ns
9 ns
tVP e tC b 5
Hold of Address Valid after
ALE Falling Edge
11 ns
tARR e tC b 5
ALE Falling Edge to RD Falling Edge
11
tACC e tC a WS b 32
Data Input Valid after Address Output Valid
100
tRD e tC a WS b 39
Data Input Valid after RD Falling Edge
60
tRW e tC a WS b 14
RD Pulse Width
85
tDR e tC b 15
Hold of Data Input Valid after
RD Rising Edge
0 35
ns
ns
ns
ns
ns
(Note 6)
tRDA e tC b 15
Bus Enable after RD Rising Edge
51
tARW e tC b 5
ALE Falling Edge to WR Falling Edge
28
tWW e tC a WS b 15
WR Pulse Width
101
tV e tC a WS b 5
Data Output Valid before WR Rising Edge
94
tHW e tC b 10
Hold of Data Valid after WR Rising Edge
7
tDAR e tC a WS b 50
Falling Edge of ALE to
Falling Edge of RDY
33
ns
ns
ns
ns
ns
ns
tRWP e tC
RDY Pulse Width
66 ns
Note CL e 40 pF
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (tCKIR and tCKIL) on CKI input less than 2 5 ns
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later tHAE may be as long as (3 tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready
input
Note 4 WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 30 MHz with
one wait state programmed
Note 5 Due to emulation restrictions actual limits will be better
Note 6 This is guaranteed by design and not tested
6

6 Page









HPC16064 pdf, datenblatt
Connection Diagrams (Continued)
Pin Grid Array Pinout
TL DD 11372 – 34
Top View
(looking down on component side of PC Board)
Order Number HPC16064XXX U20 HPC16064XXX U30 HPC16004U20 or HPC16004U30
See NS Package Number U68A
Note XXX designates the unique ROM code of a masked device
Ports A B
The highly flexible A and B ports are similarly structured
The Port A (see Figure 11 ) consists of a data register and a
direction register Port B (see Figures 12 13 and 14 ) has an
alternate function register in addition to the data and direc-
tion registers All the control registers are read write regis-
ters
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs Port pins se-
lected as inputs are placed in a TRI-STATE mode by reset-
ting corresponding bits in the direction register
A write operation to a port pin configured as an input causes
the value to be written into the data register a read opera-
tion returns the value of the pin Writing to port pins config-
ured as outputs causes the pins to have the same value
reading the pins returns the value of the data register
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN) The sec-
ondary functions are enabled by setting the corresponding
bits in the BFUN register
12

12 Page





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