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GO7007 Schematic ( PDF Datasheet ) - WIS

Teilenummer GO7007
Beschreibung Single-Chip Streaming Media Encoder
Hersteller WIS
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Gesamt 10 Seiten
		
GO7007 Datasheet, Funktion
WIS GO7007
Single-Chip Streaming
Media Encoder
The GO7007 is a monolithic multi-format video
compression chip. This high-performance chip uses
multiple algorithms to buffer and compress raw video data
into video streams. The output video stream is a versatile
GoStream™ format that can easily be transcoded by
external processors into MPEG-1, MPEG-2, MPEG-4, and
H.263 formats. The video streams are output through a
Host Parallel Interface (HPI) or a Universal Serial Bus
(USB) interface. The GO7007 is capable of delivering
streaming video up to full-D1 resolution at a full-motion
frame rate, over the Web and emerging broadband
networks. It is ideal for a wide range of encoding
applications, from DVRs/PVRs to PC/Web cameras.
Optimizing Encoding Performance
WIS Technologies’ unique encoder architecture provides
flexibility to accommodate many different ISO/ITU video
standards. The ability to output video streams in almost
any standard format greatly benefits upgrade flexibility as
standards evolve. Enabling application-level conference
bridging and legacy video streaming are additional benefits
of the WIS GO7007.
WIS GO chip integration enables a glueless logic interface
between the GO7007 and the CMOS image sensors.
Included on the chip are SDRAM and USB controllers and
I2C and HPI interfaces. Full resolution can be achieved
with 4MB PC100 SDRAM to reduce system costs.
The WIS GO7007 is a
real-time MPEG-4 video
compression chip. This high
performance encoder enables
developers to create and deliver
streaming video over the Web,
emerging broadband, and
mobile networks.
AN
I N N O VA T O R
IN
M U L T I ME D I A
CO M M UNICAT I O N






GO7007 Datasheet, Funktion
38 AD6
39 AD7
40 AD8
41 AD9
42 AD10
43 VSS_IO
44 VDD_IO
45 SDRAM_DQ7
46 VDD_CORE
47 VSS_CORE
48 SDRAM_DQ6
49 SDRAM_DQ5
50 SDRAM_DQ4
51 SDRAM_DQ3
52 VSS_IO
90 SDRAM_DQ31
91 SDRAM_DQ30
92 SDRAM_DQ29
93 SDRAM_DQ28
94 VSS_IO
95 VDD_IO
96 SDRAM_DQ27
97 SDRAM_DQ26
98 VDD_CORE
99 VSS_CORE
100 SDRAM_DQ25
101 VSS_IO
102 VDD_IO
103 SDRAM_DQ24
104 SDRAM_DQ23
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
USB+
USB-
VSS_USB
USB_CLK
PDATA0
PDATA1
PDATA2
PDATA3
VDD_CORE
VSS_CORE
PDATA4
PDATA5
PDATA6
PDATA7
HREF
194 VDD_IO
195 MXI
196 MXO
197 SYNC_HPI
198 DBG_INT
199 MCLK
200 USBRST_EN
201 RESET#
202 VDD_CORE
203 VSS_CORE
204 DEBUG_MODE
205 BIST_FAIL
206 BIST_DONE
207 BIST_RESET
208 BIST_RUN
Table 0-2 Pin Description
Symbol
PLL Pins
AVDD_MPLL
Pin #
1, 3
VSS_MPLL
DVDD_MPLL
2, 4, 5
6
MPLL_BP
8
UPLL_BP
9
MXI
MXO
MCLK
195
196
199
Built-In Self Test Pins
TEST_EN
10
Pin Type
Description
Note
Supply
Supply
Supply
Input
Input
Input
Output
Input
1.8V Analog power supply for Master clock
PLL
Ground for Master clock PLL
1.8V Digital power supply for Master clock
PLL
Master clock PLL Bypass. When pin is tied
to ground, master clock is generated by
internal PLL locked to MXI. Otherwise,
MCLK is used as master clock input.
USB clock PLL Bypass. When pin is tied to
ground, USB clock is generated by
internal PLL locked to MXI. Otherwise,
USB_CLK is used as USB clock input.
Oscillator Input
Usually connected to the crystal
Use this Master Clock input pin when
Master clock PLL is bypassed.
1
Input
Test Enable. Reserved for manufacturers’
use. Connect pin to ground under normal
operation.
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