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74LVX16373 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer 74LVX16373
Beschreibung LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE) WITH 5V TOLERANT INPUTS
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 10 Seiten
74LVX16373 Datasheet, Funktion
74LVX16373
LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)
WITH 5V TOLERANT INPUTS
s HIGH SPEED :
tPD = 5.4 ns (MAX.) at VCC = 3V
s 5V TOLERANT INPUTS
s POWER DOWN PROTECTION ON INPUTS
s INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC =3V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC =3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) at VCC =3V
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE) input is low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high imped-
ance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74LVX16373TTR
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74LVX16373 Datasheet, Funktion
74LVX16373
TEST CIRCUIT
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 1Kor equivalent
RT = ZOUT of pulse generator (typically 50)
SWITCH
Open
VCC
GND
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
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