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PDF ST16C650A Data sheet ( Hoja de datos )
| Número de pieza | ST16C650A | |
| Descripción | 2.90V TO 5.5V UART WITH 32-BYTE FIFO | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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JANUARY 2004
GENERAL DESCRIPTION
The ST16C650A1 (650A) is a 2.90 to 5.5 volt
Universal Asynchronous Receiver and Transmitter
(UART) with 5 volt tolerant inputs. This device
supports Intel and PC ISA mode data bus interfaces
and is software compatible to industry standard
16C450, 16C550, ST16C580 and ST16C650A
UARTs.
The 650A has 32 bytes of TX and RX FIFOs and is
capable of operating up to serial data rates of 3.125
Mbps at 5 volt supply voltage. The internal registers
include the 16C550 register set plus Exar’s enhanced
registers for additional features to support today’s
highly demanding data communication needs. The
enhanced features include automatic hardware and
software flow control, selectable TX and RX trigger
levels, and wireless infrared (IrDA) encoder/decoder.
The device provides a new capability to give user the
ability to program the wireless infrared encoder
output pulse width, hence reducing the power
consumption of a handheld unit.
The ST16C650A device comes in the 44-pin PLCC
and 48-pin TQFP packages in both the commercial
and industrial temperature ranges.
NOTE: 1 Covered by US patents #5,649,122.
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
FEATURES
REV. 5.0.0
Added features in top mark date code of "HC YYWW"
and newer:
s 2.90 to 5.5 Volt Operation
s 5 Volt Tolerant Inputs
s Automatic RS485 Half-Duplex Control Output
s Programmable Infrared Encoder Pulse Width
s Sleep Mode with Wake-up Indicator
s Device ID & Revision
s Up to 3.125 Mbps Data Rate at 5 Volts
Added feature in top mark date code of "I2 YYWW"
and newer:
s 0 ns address hold time
• Intel or PC Mode 8-bit Bus Interface
• 32-byte Transmit and Receive FIFOs
• Automatic Hardware (RTS/CTS) Flow Control
• Hardware Flow Control Hysteresis
• Automatic Software (Xon/Xoff) Flow Control
APPLICATIONS
• Battery Operated Electronics
• Handheld Terminal
• Personal Digital Assistants
• Cellular Phones DataPort
• Wireless Infrared Data Communications Systems
FIGURE 1. BLOCK DIAGRAM
RESET
A2:A0
D7:D0
IOR#
IOR
IOW#
IOW
CS2#
CS1
CS0
INT
TXRDY#
RDRDY#
DDIS#
SEL
S1
S2
S3
IRQA
IRQB
IRQC
Intel,
Motorola
or PC
Data Bus
Interface
PC Mode:
COM 1 to 4
Decode Logic
UART
Configuration
Regs
BRG
Prescaler
32 Byte TX FIFO
Transmitter
Infrared Encoder and
Pulse Width Control
CTS Flow
Control
Modem Control Signals
RTS Flow
Control
Infrared
Decoder
Receiver with Auto
Software Flow Control
32 Byte RX FIFO
Baud Rate Generator
Crystal Osc/Buffer
TX
DTR#, DSR#,
RTS#, CTS#,
CD#, RI#
RX
XTAL1/CLK
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
NAME
40- 44- 48-
PDIP PLCC TQFP
PIN # PIN # PIN #
TYPE
DESCRIPTION
AEN#
- 28 24 I Address Enable input (active low)
When AEN# transition to logic 0, it decodes and validates COM 1-4 ports
address per S1, S2 and S3 inputs.
S1 - 23 21 I Select 1 to 3
S2 - 10 5
These are the standard PC COM 1-4 ports and IRQ selection inputs. See
S3 - 35 31
Table 1 and Table 3 for details. The S1 pin has an internal 100kΩ pull-up
resistor.
IRQA
IRQB
IRQC
- 33 30 O Interrupt Request A, B and C Outputs (active high, tri-state)
- 32 29
These are the interrupt outputs associated with COM 1-4 to be connected
- 27 23
to the host data bus. See interrupt section for details. The Interrupt
Requests A, B or C functions as IRQx to the PC bus. IRQx is enabled by
setting MCR bit-3 to logic 1 and the desired interrupt(s) in the interrupt
enable register (IER).
LPT1#
- 17 12 O Line Printer Port-1 Decode Logic Output (active low)
This pin functions as the PC standard LPT-1 printer port address decode
logic output, see Table 1. The baud rate generator clock output, BAUD-
OUT#, is internally connected to the RCLK input in the PC mode.
LPT2#
- 26 22 O Line Printer Port-2 Decode Logic Output (active low)
This pin functions as the PC standard LPT-2 printer port address decode
logic output, see Table 1.
MODEM OR SERIAL I/O INTERFACE
TX
11 13
8
O Transmit Data or wireless infrared transmit data
This output is active low in normal standard serial interface operation (RS-
232, RS-422 or RS-485) and active high in the infrared mode. Infrared
mode can be enabled by connecting pin ENIR to VCC or through software
setting after power up.
RX
10 11
7
I Receive Data or wireless infrared receive data
Normal received data input idles at logic 1 condition and logic 0 in the
infrared mode. The wireless infrared pulses are applied to the decoder.
This input must be connected to its idle logic state in either normal, logic 1,
or infrared mode, logic 0, else the receiver may report “receive break” and/
or “error” condition(s).
RTS#
32 36 32
O Request to Send or general purpose output (active low)
This port may be used for one of two functions:
1) automatic hardware flow control, see EFR bit-6, MCR bit-1and IER bit-
6.
2) RS485 half-duplex direction control, see XFR bits 2 and 5.
RTS# output must be asserted before auto RTS flow control can start.
CTS#
36 40 38
I Clear to Send or general purpose input (active low)
If used for automatic hardware flow control, data transmission will be
stopped when this pin is de-asserted and will resume when this pin is
asserted again. See EFR bit-7 and IER bit-7.
DTR#
33 37 33
O Data Terminal Ready or general purpose output (active low)
DSR#
37 41 39
I Data Set Ready input or general purpose input (active low)
5
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REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
2.2 5-Volt Tolerant Inputs
The 650A can acccept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 650A is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Figure 13). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device.
2.4 Device Identification and Revision
The ST16C650A provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x04 for the
ST16C650A and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.5 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# and TXRDY# output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 650A is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 650A
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures 24 through 29.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR BIT-3 = 0
(DMA MODE DISABLED)
FCR BIT-3 = 1
(DMA MODE ENABLED)
RXRDY# 0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
11
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| PDF Descargar | [ Datasheet ST16C650A.PDF ] | |
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