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PDF ST16C552 Data sheet ( Hoja de datos )
| Número de pieza | ST16C552 | |
| Descripción | DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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ST16C552
ST16C552A
DUAL UART WITH 16-BYTE FIFO AND
PARALLEL PRINTER PORT
DESCRIPTION
December 2003
The ST16C552/ST16C552A (552/552A) is a dual universal asynchronous receiver and transmitter (UART) with
an added bi-directional parallel port that is directly compatible with a CENTRONICS type printer. The parallel port
is designed such that the user can configure it as general purpose I/O interface, or for connection to other printer
devices. The 552/552A provides enhanced UART functions with 16 byte FIFO’s, a modem control interface, and
data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status.
The system interrupts and control may be tailored to meet user requirements. An internal loop-back capability
allows onboard diagnostics. A programmable baud rate generator is provided to select transmit and receive clock
rates from 50 bps to 1.5 Mbps. The 552/552A is available in a 68 pin PLCC package. The 552/552A is compatible
with the 16C450 and 16C550. The difference between the ST16C552 and ST16C552A is the logic state of the
printer port, INTP interrupt. The INTP interrupt is active high (logic 1) on the ST16C552 whereas INTP is active
low (logic 0) on the ST16C552A part when the interrupt latch mode is selected. The 552/552A is fabricated in an
advanced CMOS process with power down mode to reduce the power consumption. The 552A does not support
the power down mode.
FEATURES
PLCC Package
Added features in device revision "F" and newer:
• 5V Tolerant Inputs
• Pin to pin and functional compatible to ST16C452/
452PS, TL16C552
• 2.97 to 5.5 volt operation
• Software compatible with INS8250, NS16C550
• 1.5 Mbps transmit/receive operation (24MHz)
• 16 byte transmit FIFO
• 16 byte receive FIFO with error flags
• Independent transmit and receive control
• Modem and printer status registers
• UART port and printer port Bi-directional
• Printer port direction set by single control bit or 8 bit
pattern (AA/55)
• Modem control signals (-CTS, -RTS, -DSR, -DTR,
-RI, -CD)
• Programmable character lengths (5, 6, 7, 8)
• Even, odd, or no parity bit generation and detection
• TTL compatible inputs, outputs
• Power down mode
TXB 10
-DTRB 11
-RTSB 12
-CTSB 13
D0 14
D1 15
D2 16
D3 17
D4 18
D5 19
D6 20
D7 21
-TXRDYA 22
VCC 23
-RTSA 24
-DTRA 25
TXA 26
ST16C552CJ68
ST16C552ACJ68
60 INTB
59 INTP
58 -SLCTIN
57 INIT
56 -AUTOFDXT
55 -STROBE
54 GND
53 PD0
52 PD1
51 PD2
50 PD3
49 PD4
48 PD5
47 PD6
46 PD7
45 INTA
44 RDOUT
ORDERING INFORMATION
Part number
ST16C552CJ68
ST16C552ACJ68
ST16C552IJ68
ST16C552AIJ68
Pins
68
68
68
68
Package
PLCC
PLCC
PLCC
PLCC
Operating temperature
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
Device Status
Active
Active
Active
Active
Rev. 3.40
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
1 page  
ST16C552/552A
SYMBOL DESCRIPTION
Symbol
-IOR
-IOW
PD7-PD0
PE
RDOUT
-RESET
-RXRDY A/B
Rev. 3.40
Pin
37
36
46-53
67
44
39
9,61
Signal Type
Pin Description
trailing edge of -IOR (end of the external CPU read cycle).
I Read strobe.- A logic 0 transition on this pin will place the
contents of an Internal register defined by address bits A0-
A2 for either UART channels A/B or A0-A1 for the printer
port, onto D0-D7 data bus for a read cycle by an external
CPU.
I Write strobe.- A logic 0 transition on this pin will transfer the
data on the internal data bus (D0-D7), as defined by either
address bits A0-A2 for UART channels A/B or A0-A1 for the
printer port, into an internal register during a write cycle from
an external CPU.
I/O Printer Data port (Bi-directional three state) - These pins are
the eight bit, three state data bus for transferring information
to or from an external device (usually a printer). D0 is the
least significant bit. PD7-PD0 are latched during a write
cycle (output mode).
I Paper Empty - General purpose input or line printer paper
empty (Internal pull-up). This pin can be connected to
provide a printer out of paper indication.
O Read Out (active high) - This pin goes to a logic 1 when the
external CPU is reading data from the 552/552A. This signal
can be used to enable/disable external transceivers or other
logic functions.
I Master Reset (active low) - a logic 0 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C552/552A External Reset Conditions for
initialization details.)
O Receive Ready A/B (active low). This function is associated
with the dual channel UARTs and provide the RX FIFO/
RHR status for individual receive channels (A-B). A logic 0
indicates there is receive data to read/unload, i.e., receive
ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is
empty or when the programmed trigger level has not been
5
5 Page 
ST16C552/552A
FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6/
7 but not the transmit trigger level. The transmit
interrupt trigger level is set to 16 following a reset. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Hardware/Software and Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must be
taken when handling these interrupts. Following a reset
the transmitter interrupt is enabled, the 552/552A will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
to continuing operations. The LSR register provides the
current singular highest priority interrupt only. It could
be noted that CTS and RTS interrupts have lowest
interrupt priority. A condition can exist where a higher
priority interrupt may mask the lower priority CTS/RTS
interrupt(s). Only after servicing the higher pending
interrupt will the lower priority CTS/ RTS interrupt(s) be
reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 552/552A FIFO may hold more
characters than the programmed trigger level. Follow-
ing the removal of a data byte, the user should recheck
LSR bit-0 for additional characters. A Receive Time
Out will not occur if the receive FIFO is empty. The time
out counter is reset at the center of each stop bit
received or each time the receive holding register (RHR)
is read (see Figure 4, Receive Time-out Interrupt). The
actual time out value is T (Time out length in bits) = 4 X
P (Programmed word length) + 12. To convert the time
out value to a character value, the user has to consider
the complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T = 4 X 7(programmed word length) + 12 = 40 bit times.
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
Programmable Baud Rate Generator
The 552/552A supports high speed modem technolo-
gies that have increased input data rates by employing
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbps input data rate. A 128.0Kbps ISDN modem
that supports data compression may need an input
data rate of 460.8Kbps. The 552/552A can support a
standard data rate of 921.6Kbps.
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
The 552/552A requires that an external clock source
be connected to the CLK input pin to clock the internal
baud rate generator for standard or custom rates. (see
Baud Rate Generator Programming below).
The generator divides the input 16X clock by any divisor
from 1 to 216 -1. The 552/552A divides the basic external
clock by 16. The basic 16X clock provides table rates to
support standard and custom applications using the
Rev. 3.40
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST16C552.PDF ] | |
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