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PDF PIC16F84A Data sheet ( Hoja de datos )
| Número de pieza | PIC16F84A | |
| Descripción | 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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 1. - 8-Bit Microcontroller - Microchip  Hay una vista previa y un enlace de descarga de PIC16F84A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PIC16F84A
18-pin Enhanced FLASH/EEPROM 8-Bit Microcontroller
High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single-cycle except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 1024 words of program memory
• 68 bytes of Data RAM
• 64 bytes of Data EEPROM
• 14-bit wide instruction words
• 8-bit wide data bytes
• 15 Special Function Hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes
• Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB<7:4> interrupt-on-change
- Data EEPROM write complete
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 25 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• 10,000 erase/write cycles Enhanced FLASH
Program memory typical
• 10,000,000 typical erase/write cycles EEPROM
Data memory typical
• EEPROM Data Retention > 40 years
• In-Circuit Serial Programming™ (ICSP™) - via
two pins
• Power-on Reset (POR), Power-up Timer (PWRT),
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip RC
Oscillator for reliable operation
• Code protection
• Power saving SLEEP mode
• Selectable oscillator options
Pin Diagrams
PDIP, SOIC
RA2
RA3
RA4/T0CKI
MCLR
VSS
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
18 RA1
17 RA0
16 OSC1/CLKIN
15 OSC2/CLKOUT
14 VDD
13 RB7
12 RB6
11 RB5
10 RB4
SSOP
RA2
RA3
RA4/T0CKI
MCLR
VSS
VSS
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
20 RA1
19 RA0
18 OSC1/CLKIN
17 OSC2/CLKOUT
16 VDD
15 VDD
14 RB7
13 RB6
12 RB5
11 RB4
CMOS Enhanced FLASH/EEPROM
Technology:
• Low power, high speed technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 5.5V
- Industrial: 2.0V to 5.5V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 15 A typical @ 2V, 32 kHz
- < 0.5 A typical standby current @ 2V
2001-2013 Microchip Technology Inc.
DS35007C-page 1
1 page  
2.0 MEMORY ORGANIZATION
There are two memory blocks in the PIC16F84A.
These are the program memory and the data memory.
Each block has its own bus, so that access to each
block can occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 3.0.
Additional information on device memory may be found
in the PIC® Mid-Range Reference Manual, (DS33023).
2.1 Program Memory Organization
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F84A, the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 2-1). Accessing a loca-
tion above the physically implemented address will
cause a wraparound. For example, for locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h,
the instruction will be the same.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
PIC16F84A
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK - PIC16F84A
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 8
RESET Vector
0000h
Peripheral Interrupt Vector 0004h
3FFh
1FFFh
2001-2013 Microchip Technology Inc.
DS35007C-page 5
5 Page 
PIC16F84A
2.4 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. If the pro-
gram counter (PC) is modified or a conditional test is
true, the instruction requires two cycles. The second
cycle is executed as a NOP. All updates to the PCH reg-
ister go through the PCLATH register.
2.4.1 STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.5 Indirect Addressing; INDF and
FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2:
movlw
movwf
NEXT clrf
incf
btfss
goto
CONTINUE
:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16F84A.
2001-2013 Microchip Technology Inc.
DS35007C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC16F84A.PDF ] | |
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