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PDF ISPLSI2128V Data sheet ( Hoja de datos )
| Número de pieza | ISPLSI2128V | |
| Descripción | 3.3V High Density Programmable Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispLSI® 2128V
3.3V High Density Programmable Logic
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 128 I/O Pin Version is Fuse Map Compatible
with 5V ispLSI 2128
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 80 MHz Maximum Operating Frequency
— tpd = 10 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram*
Output Routing Pool (ORP)
D7 D6 D5 D4
Output Routing Pool (ORP)
D3 D2 D1 D0
A0 C7
A1 C6
A2
DQ
C5
A3 C4
DQ
Logic
A4
Array
DQ
GLB
C3
A5 C2
DQ
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3
Output Routing Pool (ORP)
B4 B5 B6 B7
Output Routing Pool (ORP)
*128 I/O Version Shown
Description
0139A/2128V
The ispLSI 2128V is a High Density Programmable Logic
Device available in 128 and 64 I/O-pin versions. The
device contains 128 Registers, eight Dedicated Input
pins, three Dedicated Clock Input pins, two dedicated
Global OE input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 2128V features in-
system programmability through the Boundary Scan
Test Access Port (TAP). The ispLSI 2128V offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2128V device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2128v_14
1
1 page  
Specifications ispLSI 2128V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass
A 2 Data Propagation Delay
A 3 Clock Frequency with Internal Feedback 3
–
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
– 5 Clock Frequency, Max. Toggle
– 6 GLB Reg. Setup Time before Clock, 4 PT Bypass
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
twh – 18 External Synchronous Clock Pulse Duration, High
twl – 19 External Synchronous Clock Pulse Duration, Low
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
-80 -60
UNITS
MIN. MAX. MIN. MAX.
– 10.0 – 15.0 ns
– 15.0 – 20.0 ns
80.0 – 61.7 – MHz
64.5 – 51.3 – MHz
100 – 71.4 – MHz
7.0 – 9.0 –
ns
– 6.5 – 8.5 ns
0.0 – 0.0 –
ns
9.0 – 11.0 –
ns
– 7.5 – 9.5 ns
0.0 – 0.0 –
ns
– 14.0 – 16.0 ns
7.0 – 8.0 –
ns
– 15.0 – 18.0 ns
– 15.0 – 18.0 ns
– 10.0 – 12.0 ns
– 10.0 – 12.0 ns
5.0 – 7.0 –
ns
5.0 – 7.0 –
ns
Table 2-0030/2128V
5
5 Page 
Pin Configuration
ispLSI 2128V 176-Pin TQFP Pinout Diagram
Specifications ispLSI 2128V
I/O 113
VCC
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
1NC
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
1NC
IN 7
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
1NC
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1NC
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
VCC
I/O 14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ispLSI 2128V
Top View
132 I/O 78
131 VCC
130 I/O 77
129 I/O 76
128 I/O 75
127 I/O 74
126 I/O 73
125 I/O 72
124 NC1
123 I/O 71
122 I/O 70
121 I/O 69
120 I/O 68
119 I/O 67
118 I/O 66
117 I/O 65
116 I/O 64
115 NC1
114 IN 4
113 Y1
112 NC1
111 VCC
110 GOE 0
109 GND
108 Y2
107 TCK/IN 3
106 NC1
105 I/O 63
104 I/O 62
103 I/O 61
102 I/O 60
101 I/O 59
100 I/O 58
99 I/O 57
98 I/O 56
97 NC1
96 I/O 55
95 I/O 54
94 I/O 53
93 I/O 52
92 I/O 51
91 I/O 50
90 VCC
89 I/O 49
1. NC pins are not to be connected to any active signals, VCC or GND.
176-TQFP/2128V
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISPLSI2128V.PDF ] | |
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