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PDF NM9715 Data sheet ( Hoja de datos )
| Número de pieza | NM9715 | |
| Descripción | PCI Dual 1284 Printer Ports | |
| Fabricantes | MosChip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NM9715 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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Nm9715
PCI Dual 1284 Printer Ports
Features
• Single 5V operation
• Low power
• Pin-to-pin compatible to Nm9705
• PCI compatible dual 1284 printer port
• Multi-mode compatible controller (SPP, PS2, EPP,
ECP)
• Fast data rates up to 1.5 Mbytes/s (parallel port)
• Re-map function for legacy ports
• 16-byte FIFO (parallel)
• Microsoft Windows compatible registers
• Software programmable mode selects
• 128-pin QFP package
Applications
• Printer server
• Portable backup units
• Printer interface
• Add-on I/O cards
Application Notes
• AN-9715
General Description
Ordering Information
The Nm9715 is a dual 1284 parallel port controller with
PCI bus interface. Nm9715 fully supports the existing
Centronics printer interface as well as PS/2, EPP, and
ECP modes.
Commercial Grade
Nm9715CV
128-QFP 0° C to +70° C
The Nm9715 is ideally suited for PC applications, such
as high speed parallel ports. The Nm9715 is available
in a 128-pin QFP package. It is fabricated using an ad-
vanced submicron CMOS process to achieve low drain
power and high speed requirements.
MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708
1 page  
Nm9715
PCI Dual 1284 Printer Ports
Pin Name 128
nSERR
30
PAR
31
nC/BE3
8
nC/BE2 22
nC/BE1 32
nC/BE0 43
nINTA
120
EE-CS
115
EE-CLK
EE-DI
EE-DO
EE-EN
116
118
117
123
SLCTB
SLCTA
68
84
Type
O
I/O
I
I
I
I
O
O
O
I
O
I
Description
System Error (open drain). This pin goes low when address parity errors are
detected.
Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable
and valid one clock after the address phase. For data phase, PAR is stable
and valid one clock after either nIRDY is asserted on a write transaction, or
nTRDY is asserted on a read transaction.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE3 applies to byte “3”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE2 applies to byte “2”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE1 applies to byte “1”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used
as byte enables. nC/BE0 applies to byte “0”.
PCI active low interrupt output (open-drain). This signal goes low (active)
when an interrupt condition occurs.
External EEprom chip select (active high). After power on reset, Nm9715
reads the EEprom and loads the read-only configuration registers sequen-
tially from the first 64 bytes in the EEprom.
External EEprom clock.
External EEprom data input.
External EEprom data output.
Enable/Disable external EEprom (active high, internal pull-up). External
EEprom can be disabled when this pin is tied to GND or pulled low. When
external EEprom is disabled, the default values for Nm9715 will be loaded
into PCI configuration register.
I Peripheral/printer selected (internal pull-up). This pin is set to high by periph-
eral/printer when it is selected.
Rev. 1.2
Page 5
5 Page 
Nm9715
PCI Dual 1284 Printer Ports
Data Register
Data register is cleared at initialization by RESET. Dur-
ing a write operation, the data register latches the con-
tents of the data bus with the rising edge of the nIOW
input. The contents of this register are buffered and
output onto the PD7-PD0 ports. During a read opera-
tion PD7-PD0 ports are buffered and output to the host
CPU on the falling edge of the nIOR input.
Device Status Register
The contents of this register are latched for the dura-
tion of the nIOR cycle. The bits of the status port are
defined as follows.
DSR Bit-0:
0 = Normal.
1 = 10µs timeout (EPP mode only). Cleared by writing 1
into DSR register or consecutive reads (after the first
read) always returns to “0”.
DSR Bit-1:
Not used, set to “0”.
DSR Bit-2:
0 = nACK input pin is at low state (INT follows the nACK
pin) when SPP mode is selected. Normal (no interrupt)
when PS/2 mode is selected.
1 = Normal (no interrupt). In standard mode operation,
INT is active (interrupt is generated on the rising edge
of the nACK). It is cleared when DSR is read.
DSR Bit-3:
0 = Printer reports error condition.
1 = Normal operation.
DSR Bit-4:
0 = Printer is off line.
1 = Printer is on line.
DSR Bit-5:
0 = Normal operation
1 = Paper end/empty is detected
DSR Bit-7:
0 = nBUSY pin is high, printer is not ready to take data.
1 = nBUSY pin is low, printer is read to take data.
Device Control Register
DCR Bit-0:
0 = Sets the nSTROBE pin to high.
1 = Sets the nSTROBE pin to low. PD7-PD0 data are
latched into printer
DCR Bit-1:
0 = Sets the nAUTOFD pin to high. Printer generates
auto line feed after each line is printed.
1 = Sets the nAUTOFD pin to low. No auto feed func-
tion.
DCR Bit-2:
0 = Sets the INIT pin to high.
1 = Sets the INIT pin to low. Peripheral/printer starts its
initialization routine.
DCR Bit-3:
0 = Sets the nSLCTIN pin to high. Selects the printer.
1 = Sets the nSLCTIN pin to low. Printer is not selected.
DCR Bit-4:
0 = Disables Printer interrupt function. nACK pin has
no effect on the INT pin.
1 = Enables Printer interrupt function. The INT follows
the nACK input pin during standard mode, latches high
on the rising edge of the nACK when PS/2 mode is se-
lected.
DCR Bit-5:
0 = PD7-PD0 pins are out put mode.
1 = PD7-PD0 pins are input mode.
DCR Bits 7-6:
Not used, set to “0”.
Config-A Register
DSR Bit-6:
0 = State of the nACK pin (ACK = low).
1 = State of the nACK pin (ACK = high).
Configuration A register (read only). Reading this regis-
ter returns 10010100. Writing to this register has no
effect and the data is ignored.
Rev. 1.2
Page 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NM9715.PDF ] | |
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