PDF MSM5117400D Data sheet ( Hoja de datos )

Número de pieza	MSM5117400D
Descripción	DRAM / FAST PAGE MODE TYPE
Fabricantes	OKI electronic componets
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No Preview Available ! Semiconductor MSM5117400D 4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE This version: Jun. 2000 DESCRIPTION The MSM5117400D is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM5117400D achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117400D is available in a 26/24-pin plastic SOJ, 26/24-pin plastic TSOP. FEATURES • 4,194,304-word × 4-bit configuration • Single 5V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 2048 cycles/32 ms • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/24-pin 300mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM5117400D-xxSJ) 26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-1.27-K) (Product : MSM5117400D-xxTS-K) xx : indicates speed rank. PRODUCT FAMILY Family MSM5117400D-50 MSM5117400D-60 MSM5117400D-70 Access Time (Max.) tRAC 50ns tAA 25ns tCAC 13ns tOEA 13ns 60ns 30ns 15ns 15ns 70ns 35ns 20ns 20ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90ns 550mW 110ns 495mW 5.5mW 130ns 440mW 1/14 1 page DC Characteristics MSM5117400D (VCC = 5V ± 10%, Ta = 0°C to 70°C) Parameter Symbol Condition Output High Voltage VOH IOH = −5.0mA Output Low Voltage VOL IOL = 4.2mA Input Leakage Current 0V ≤ VI ≤ 6.5V ; ILI All other pins not under test = 0V Output Leakage Current DQ disable ILO 0V ≤ VO ≤ VCC MSM5117400 MSM5117400 MSM5117400 D-50 D-60 D-70 Unit Note Min. Max Min. Max Min. Max 2.4 VCC 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 0 0.4 V −10 10 −10 10 −10 10 µA −10 10 −10 10 −10 10 µA Average Power Supply Current (Operating) RAS, CAS cycling, ICC1 tRC = Min.  100  90  80 mA 1,2 Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC2 RAS, CAS = VIH RAS, CAS ≥ VCC – 0.2V ICC3 RAS cycling, CAS = VIH, tRC = Min. ICC5 RAS = VIH, CAS = VIL, DQ = enable RAS = cycling, ICC6 CAS before RAS ICC7 RAS = VIL, CAS cycling, tPC = Min. 222 mA 1 111  100  90  80 mA 1,2  5  5  5 mA 1  100  90  80 mA 1,2  80  70  60 mA 1,3 Notes: 1. 2. 3. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. 5/14 5 Page MSM5117400D • Fast Page Mode Cycle RAS VIH VIL CAS VIH VIL tCRP tASR tRCD tRAD tCSH tRAH tASC tCAS tCAH tRASP tPC tRHCP tRP tCP tCP tRSH tCAS tCAS tCRP tASC tCAH tASC tRAL tCAH Address VIH VIL Row tRCS Column tRCH Column tRCS tRCH Column tRCS tRCH WE VIH VIL OE VIH VIL DQ VOH VOL tAA tOEA tAA tOEA tAA tOEA tRRH tRAC tCAC tCLZ tCPA tOFF tOEZ Valid Data-out tCAC tCLZ tCPA tOFF tOEZ Valid Data-out tCAC tCLZ tOFF tOEZ Valid Data-out “H” or “L” • Fast Page Mode Write Cycle (Early Write) RAS VIH VIL CAS VIH VIL Address VIH VIL WE VIH VIL DQ VIH VIL tCRP tASR tRCD tRAD tRAH tASC tCAS tCSH tCAH Row Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tRASP tPC tCP tCAS tRHPC tCP tRSH tCAS tRP tCRP tASC tCAH Column tCWL tWCS tWCH tWP tASC tRAL tCAH Column tWCS tCWL tRWL tWP tWCH tDS tDH Valid Data-in tDS tDH Valid Data-in Note: OE = “H” or “L” “H” or “L” 11/14 11 Page

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