PDF MSM514256C Data sheet ( Hoja de datos )

Número de pieza	MSM514256C
Descripción	DRAM / FAST PAGE MODE TYPE
Fabricantes	OKI electronic componets
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No Preview Available ! E2G0010-17-41 ¡ Semiconductor¡ Semiconductor This veMrsSioMn5:1J4a2n5. 61C99/8CL Previous version: May 1997 MSM514256C/CL 262,144-Word ¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514256C/CL is a 262,144-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514256C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM514256C/CL is available in a 20-pin plastic DIP, 26/20-pin plastic SOJ, or 20-pin plastic ZIP. The MSM514256CL (the low-power version) is specially designed for lower-power applications. FEATURES • 262,144-word ¥ 4-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 20-pin 300 mil plastic DIP (DIP20-P-300-2.54-W1) (Product : MSM514256C/CL-xxRS) 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514256C/CL-xxJS) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514256C/CL-xxZS) xx indicates speed rank. PRODUCT FAMILY Family MSM514256C/CL-45 MSM514256C/CL-50 MSM514256C/CL-60 MSM514256C/CL-70 Access Time (Max.) Cycle Time Power Dissipation tRAC tAA tCAC tOEA (Min.) Operating (Max.) Standby (Max.) 45 ns 24 ns 14 ns 14 ns 90 ns 468 mW 50 ns 26 ns 14 ns 14 ns 100 ns 446 mW 5.5 mW/ 60 ns 30 ns 15 ns 15 ns 120 ns 385 mW 1.1 mW (L-version) 70 ns 35 ns 20 ns 20 ns 130 ns 330 mW 1/17 1 page ¡ Semiconductor MSM514256C/CL DC Characteristics (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Symbol Condition MSM514256 MSM514256 MSM514256 MSM514256 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. Output High Voltage Output Low Voltage Input Leakage Current VOH IOH = –5.0 mA 2.4 VCC 2.4 VCC 2.4 VCC 2.4 VCC V VOL IOL = 4.2 mA 0 0.4 0 0.4 0 0.4 0 0.4 V 0 V £ VI £ 6.5 V; ILI All other pins not –10 10 –10 10 –10 10 –10 10 mA under test = 0 V DQ disable Output Leakage Current ILO 0 V £ VO £ 5.5 V –10 10 –10 10 –10 10 –10 10 mA Average Power Supply Current (Operating) RAS, CAS cycling, ICC1 tRC = Min. — 85 — 80 — 70 — 60 mA 1, 2 Power Supply Current (Standby) Average Power RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, —2—2—2—2 — 1 — 1 — 1 — 1 mA 1 — 200 — 200 — 200 — 200 mA 1, 5 Supply Current (RAS-only Refresh) Power Supply Current (Standby) ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable — 85 — 80 — 70 — 60 mA 1, 2 — 5 — 5 — 5 — 5 mA 1 Average Power Supply Current ICC6 (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC7 Average Power Supply Current ICC10 (Battery Backup) RAS cycling, CAS before RAS RAS = VIL, CAS cycling, tPC = Min. tRC = 125 ms, CAS before RAS, tRAS £ 1 ms — 85 — 80 — 70 — 60 mA 1, 2 — 80 — 75 — 65 — 55 mA 1, 3 — 300 — 300 — 300 — 300 mA 1, 2, 4, 5 Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 4. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. 5. L-version. 5/17 5 Page ¡ Semiconductor MSM514256C/CL Fast Page Mode Read Cycle RAS VIH VIL – – CAS VIH VIL – – VIH – ,,,AddressVIL– tAR tCRP tRCD tASR tRAD tRAH tASC tCAS tCSH tCAH Row Column tRCS tRASP tPC tCP tCAS tASC tCAH tRHCP tRSH tCP tCAS tRAL tASC tCAH Column tRCH tRCS tRCH Column tRCS tRP tCRP tRCH WE VIH VIL – – OE VIH VIL – – DQ VOH – VOL – tAA tOEA tAA tCPA tOEA tAA tCPA tOEA tRRH tCAC tRAC tOFF tOEZ Valid tCLZ Data-out tCAC tCLZ tOFF tOEZ Valid Data-out tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) ,RAS VIH VIL – – CAS VIH – VIL – VIH – ,,,AddressVIL– tAR tCRP tRCD tCAS tASR tCSH tRAH tASC tCAH Row Column tRAD tCWL tRASP tPC tCP tCAS tASC tCAH Column tCWL tRHCP tRSH tCP tCAS tASC tCAHtRAL Column tRWL tRP tCRP WE VIH VIL – – tWCS tWCH tWP tWCR tWCS tWCH tWP tWCS tCWL tWCH tWP tDS tDH tDS tDH tDS tDH DQ VIH VIL – – Valid Data-in tDHR Valid Data-in Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/17 11 Page

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