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STLC5444 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer STLC5444
Beschreibung QUAD FEEDER POWER SUPPLY
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 17 Seiten
STLC5444 Datasheet, Funktion
STLC5444
QUAD FEEDER POWER SUPPLY
SUPPLIES POWER FOR UP TO FOUR DIGI-
TAL TELEPHONE LINES
CONFORMS TO THE CCITT RECOMMEN-
DATIONS FOR POWER FEED AT THE S OR
T REFERENCE POINTS
SUPPORTS POINT-TO-POINT AND POINT
TO MULTIPOINT CONFIGURATIONS
EACH OF THE FOUR LINES IS INDIVIDU-
ALLY CONTROLLED
HIGH-VOLTAGE BCD TECHNOLOGY SUP-
PORTING UP TO -130V
AUTOMATIC THERMAL SHUTDOWN
STATUS CONDITION DETECTION (BY MI-
CROPROCESSOR) FOR EACH LINE:
– Low output voltage
– Openloop
– Current overload
– Thermal overload
– Normal line condition
PROGRAMMABLE CURRENT LIMITING
OUTPUT CURRENT UP TO 120mA
DIP24
PLCC44
ORDERING NUMBERS: STLC5444B1 (DIP24)
STLC5444FN (PLCC44)
DIP24 PIN CONNECTION (Top view)
DESCRIPTION
The ISDN Quad Feeder Power Supply (IQFPS)
provides a power source for up to four line inter-
faces. The power source to the device is a local
battery or a centralized regulated power supply.
It can operate in point-to-point and point-to-mul-
tipoint configurations as far as S interface is con-
cerned.
By the device microprocessor interface, each
powered line is individually controlled and moni-
tored.
Therefore, overloads and faults are easy to detect
and localize even in a large system.
The status conditions detected by the device on
each line that may be read by the microprocessor
are :
low output voltage
openloop
current overload
thermal overload
normal line conditions
A hardware current limiting programmable feature
is available.
D1
D0
INT
BGND
VCC
ILIM
N.C.
VBB
N.C.
S0
S1
VBB
1
2
3
4
5
6
7
8
9
10
11
12
24 D2
23 D3
22 A0
21 DGND
20 ALE
19 WR
18 CS
17 RD
16 RESET
15 S3
14 RSRVD
13 S2
D94TL102
December 1997
1/17






STLC5444 Datasheet, Funktion
STLC5444
SWITCHING CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified)
MICROPROCESSOR READ/WRITE TIMING NON MULTIPLEXED MODE (for references see figure 1a
and 2b).
Symbol
Parameter
Min.
tRLRH
tRHRL
tRLDA
tRHDZ
tASRL
tAHRH
tASWL
tAHWH
tADDA
tWLWH
tWHWL
tDAWH
tWHDZ
tRES
RD, CS pulse width
RD, recovery time
T amb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
RD, CS low to data available
RD or CS high to data Z
Tamb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
Address setup time to READ active
Address hold time to READ inactive
Address setup time to WRITE active
Addess hold time to WRITE inactive
Address stable to data available
Tamb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
WR or CS pulse width
Write recovery time
Data setup time
Data hold time
T amb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
Reset Pulse with
260
200
220
0
0
30
50
360
390
200
200
100
20
40
200
Note: AC timings are tested at 0.8V and 2V with input levels of 0.4V and 2.4V.
Max.
260
130
160
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified)
MICROPROCESSOR READ/WRITE TIMING MULTIPLEXED MODE (for references see figure 1 and 2).
Symbol
Parameter
Min.
tRLRH
tRHRL
tRLDA
tRHDZ
tAHAL
tADAL
tADAZ
tAZRL
tAZWL
tADDA
tWLWH
tWHWL
tDAWH
tWHDZ
tRES
RD, CS pulse width
RD, recovery time
T amb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
RD, CS low to data available
RD or CS high to data Z
Tamb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
ALE pulse width
Address setup time
Address hold time
Address Z to RD low
Address Z to WR Low
Address stable to data available
Tamb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
WR or CS pulse width
Write recovery time
Data setup time
Data hold time
T amb: 0 to 70°C
T amb: -40 to 0°C and +70°C to +85°C
Reset Pulse with
260
200
220
100
60
50
0
0
360
390
200
200
100
20
40
200
Note: AC timings are tested at 0.8V and 2V with input levels of 0.4V and 2.4V.
Max.
260
130
160
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Si Timing (at 10% of final value)
Symbol
tEN
tDIS
Parameter
Test condition
Si output enable time (from LER)
RLOAD = 3k
Si output disable time (from LER or RESET)
Typ.
2
3
Max.
5
6
Unit
µs
µs
6/17

6 Page









STLC5444 pdf, datenblatt
STLC5444
LER :
Bit
Logical 1
Logical 0 (default value)
0
O0 on
O0 off
1
O1 on
O1 off
2
O2 on
O2 off
3
O3 on
O3 off
The Line Enable Register (LER) is used to enable or disable the individual output line drivers. The output
line will only become active if the corresponding bit in the TOR is set to a logical 1. The LER can be writ-
ten directly and read indirectly.
ABSOLUTE MAXIMUM RATINGS (TA = 0°C to 70°C)
Parameter
Voltage from Digital Input to DGND
Voltage from VCC to DGND
Voltage from VBB to DGND
100ns Pulse voltage from Si to DGND (See Notes)
Voltage from BGND to DGND
Storage Temperature
Note : Si stands for O0, O1, O2 or O3 outputs.
RECOMMENDED OPERATING CONDITIONS
Value
-0.4V to VCC
-0.4V to +7V
-130V to +0.4V
-130V to +2V
+0.5V, -3V
T = -60°C to +150°C
Parameter
(*) Ambient Temperature
for standard type
for ext. temperature type
Supply Voltage
Programmed Limiting Current
Symbol1
TA
TA
VCC
VBB
DGND
BGND
ISLIM
Min.
0
-40
4.75
-115
0
-3
Max.
70
85
5.25
-38
0
+0.5
120
Units
°C
°C
V
V
V
V
mA
Note: The test condition is specified with a diode in series with VBB.
(*): Specifications in this data sheet are guaranteed by testing from 0°C to +70°C. For extended temperature range types, performance from
–40°C to +85°C is guaranteed by characterization and periodic sampling of production units.
ORDERING TYPES:
STLC5444B1, PDIP24 package: 0 to 70°C Temperature range.
STLC5444FN, PLCC44 package: 0 to 70°C Temperature range.
STLC5444B1-X, PDIP24 package: -40 to 85°C Temperature range.
STLC5444FN-X, PLCC44 package: -40 to 85°C Temperature range.
APPLICATION HINT
In the Absolute Maximum Ratings table it is speci-
fied that the voltage applied on the -Vbat pin
should never exceed by more than 0.4V the volt-
age applied on the Ground pin.
As long as the external circuitry assures compli-
ance with the above, no more considerations are
needed.
In some cases however it may be not possible to
exclude that conditions may occur (hot insertion,
power supply transients, etc.) where the negative
supply has a transient overshoot above ground
voltage. Then a protection circuitry that clamps
such overshoot can add to the equipment reliabil-
ity. Such protection can be designed taking into
considerations that typically the devices behave
as follows:
- if the Vbat pin is not connected, and the other
pins are normally biased, the chip generates
on it an open circuit voltage of +420mV.
- if all the other pins are normally biased and
the -Vbat pin forced at +600mV, a current of
10mA flows into it. At the same time from +5V
a current of 4mA is absorbed (this low current
from +5V simply means that no parasitic
latch-ups are triggered inside the chip). No
deterioration of the device occurs.
- if all the other pins are normally biased, and
the -Vbat pin is forced at +1.5V for a transient
period, no deterioration of the device occurs.
Transient period can be considered any time
interval that lasts for less than 10µs and is not
repeated more than 5000 times during the
device lifetime.
12/17

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