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PDF STV9212 Data sheet ( Hoja de datos )
| Número de pieza | STV9212 | |
| Descripción | Video Processor for CRT Monitors with PictureBooST | |
| Fabricantes | ST Microelectronics | |
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® STV9212
Video Processor for CRT Monitors with PictureBooST™
Main Features
s General
q I²C-Bus Controlled
q Supports AC- and DC-coupled applications
q 5V to 8V Power Supply
q Matches to virtually any video amplifier
s PictureBooST™
q PictureBooST™ insertion input
q Full-screen PictureBooST™ via I²C-bus
q Context-sensitive Picture Enhancement
s Video Clamping
q Input and Output Video Clamp
q Sync Pulse Polarity Auto-rectification
q Clamp Pulse Generation timed either by sync
or video blanking pulse
s Video Processing
q Contrast Adjustment with excellent channel
matching
q Gain stages for control of white
q Two DC-mode cut-off ranges
q Output DC offset control
q Automatic Beam Limiter (ABL)
q Video Insertion Pulse (VIP), 2 levels
q Amplifier Control (Blanking and Stand-by)
s OSD Insertion with Contrast Control
s Control Output
q Amplifier Standby and Blanking Control
q 3 DAC for control of DC Restore Amplifier or
Brightness in DC-coupled system
DIP24S:(Plastic Package)
ORDER CODE: STV9212
General Description
The STV9212 is an I²C-bus controlled color video
processor designed for standard CRT monitor
applications. It can drive systems where cathodes
are either AC- or DC-coupled to the amplifier
outputs. The three video channels provide contrast
and white balance separate gain adjustments as
well as one-per-channel DC cut-off control and
common DC offset control functions. On top of
these usual controls, it features context-sensitive
picture enhancement circuitry to support the
PictureBooST™ function that enhances the
appearance of still pictures and moving video.
In AC coupling applications, the device can pilot
three cathode DC restore channels dedicated to set
CRT cut-off bias voltages and to control brightness
through cathodes.
The RGB video outputs have a class A architecture
and directly drive the amplifier channels without
unnecessarily consuming current. Bandwidth
limitation I²C-bus adjustments can contribute to
keeping the application EMI under control.
OSD (On-Screen Display) graphics are inserted by
means of a Fast Blanking signal. Independent OSD
contrast control facilitates adaptation to various
OSD generators and provides system flexibility.
The STV9212 is perfectly compatible with other ST
components for CRT video boards, such as video
amplifiers and OSD generators.
October 2003
1/34
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 page  
STV9212
2 Functional Description
Functional Description
The functional blocks are described in the order they act on the signal.
Figure 2: STV9212 Block Diagram
5/34
5 Page 
STV9212
Functional Description
2.5 OSD Insertion
The On-Screen Display (OSD) is inserted with a high level on the FBLK input (TTL). The device
acts as follows:
q The three RGB video input signals (IN1, IN2, IN3) are internally blanked, i.e. put at the black
level.
q Binary levels (TTL) on inputs OSD1, OSD2 and OSD3, after processing in the OSD contrast
stage, are added to the corresponding blanked video channels.
In this way, the OSD contents replace the video contents where the FBLK input is high. See
Figure 2 and Figure 10.
The OSD is inserted after the PictureBooST™ block and before the Drive block. As a consequence,
OSD insertion overlaps all video contents, including the PictureBooST™-ed zones. Color
temperature adjustments by means of the I²C-bus Drive registers act in the OSD insets.
The OSD contrast stage allows the adjustment of the level of OSD insets simultaneously on the
three OSD channels and independently of the video contrast adjustment. Refer to
Section 4: Electrical Specifications for values.
Figure 10: OSD Insertion
Video before
OSD insertion
Video Black Level VRef
FBLK
OSD1(2,3)
max
Video after
OSD insertion
VOSD
mid
min.
OSDCRST
Note: The OSDCRST I²C-bus field acts equally on all 3 OSD channels.
Video Black Level VRef
2.6 Drive Stage
The Drive stage is a set of three attenuators separately controlled via three I²C-bus registers,
DRIVE1, DRIVE2 and DRIVE3. It affects all signals, ordinary video, PictureBooST™ processed
video and OSD insets. It is designed to compensate for differences in gain of the three CRT
cathodes. See Figure 11 and for values, refer to Section 4: Electrical Specifications.
11/34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STV9212.PDF ] | |
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