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AD5060 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5060
Beschreibung Full Accurate 14/16 Bit Vout nanoDac Buffered
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD5060 Datasheet, Funktion
Fully Accurate 14-/16-Bit VOUT nanoDAC
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5040/AD5060
FEATURES
Single 14-/16-bit DAC, 1 LSB INL
Power-on reset to midscale or zero scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5040 and the AD5060, members of the ADI nanoDAC
family, are low power, single 14-/16-bit buffered voltage-out
DACs that operate from a single 2.7 V to 5.5 V supply. The
AD5040/AD5060 parts offer a relative accuracy specification
of ±1 LSB and operation are guaranteed monotonic with a
±1 LSB DNL specification. The parts use a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The reference for both the AD5040
and AD5060 is supplied from an external VREF pin. A reference
buffer is also provided on-chip. The AD5060 incorporates a
power-on reset circuit that ensures the DAC output powers up
to midscale or zero scale and remains there until a valid write
takes place to the device. The AD5040 and the AD5060 both
contain a power-down feature that reduces the current con-
sumption of the device to typically 330 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The parts are put into power-down mode over the serial
interface. Total unadjusted error for the parts is <2 mV.
Both parts exhibit very low glitch on power-up.
FUNCTIONAL BLOCK DIAGRAM
VREF
VDD
POWER-ON
RESET
BUF
DAC
REGISTER
REF(+)
DAC
OUTPUT
BUFFER
AD5040/
AD5060
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
AGND
SYNC SCLK DIN
DACGND
Figure 1.
PRODUCT HIGHLIGHTS
1. Available in a small, 8-lead SOT-23 package.
2. 14-/16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (midscale, zero scale).
Table 1. Related Devices
Part No. Description
AD5061 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 4 LSB INL, SOT-23
AD5062 2.7 V to 5.5 V, 16-bit nanoDAC D/A,1 LSB INL, SOT-23
AD5063 2.7 V to 5.5 V, 16-bit nanoDAC D/A, 1 LSB INL, MSOP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005-2010 Analog Devices, Inc. All rights reserved.






AD5060 Datasheet, Funktion
AD5040/AD5060
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREF to GND
Operating Temperature Range
Industrial (A, B Grade)
Extended Automotive Temperature
Range (Y Grade)
Storage Temperature Range
Maximum Junction Temperature
SOT-23 Package
Power Dissipation
θJA Thermal Impedance
θJc Thermal Impedance
Reflow Soldering (Pb-free)
Peak Temperature
Time-at-Peak Temperature
ESD (AD5040/AD5060)
Rating
−0.3 V to +7.0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
206°C/W
91°C/W
260°C
10 sec to 40 sec
1. 5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of <2 kV. It is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24

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AD5060 pdf, datenblatt
AD5040/AD5060
5.005
5.000
VREF = 5V
TA = 25°C
4.995
4.990
4.985
4.980
4.975
5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00
VDD (V)
Figure 28. Typical Output vs. Supply Voltage
CH3 = SCLK
ZERO-SCALE
1kΩ TO GND
C4 = 143mV p-p
CH4 50.0mV
M4.00μs
CH1 1.64V
Figure 31. Glitch upon Entering Software Power-Down to Zero Scale
1kΩ TO GND ZERO-SCALE
C4 = 50mV p-p
CH2 = VOUT
CH1 = TRIGGER
CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs
Figure 29. Time to Exit Power-Down to Midscale
400
350
FULL-SCALE
300
VDD = 5V
VREF = 4.096V
TA = 25°C
250
200 MID-SCALE
150
100 QUARTER-SCALE
50
0
–50
100
ZERO-SCALE
1k 10k
FREQUENCY (Hz)
100k
1M
Figure 30. Noise Spectral Density
CH4 20.0mV
M1.00μs
CH1 1.64V
Figure 32. Glitch upon Exiting Software Power-Down to Zero Scale
2T
T
3
CH3 2.00V CH2 50mV
M1.00ms
C2
25mV p-p
C3
4.96V p-p
C3 FALL
935.0μs
C3 RISE
s
NO VALID
EDGE
CH3 1.36V
Figure 33. Glitch upon Entering Hardware Power-Down to Three-State
Rev. A | Page 12 of 24

12 Page





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