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PDF DS1743 Data sheet ( Hoja de datos )
| Número de pieza | DS1743 | |
| Descripción | Y2KC Nonvolatile Timekeeping RAM | |
| Fabricantes | Dallas | |
| Logotipo |  |
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DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
Integrated NV SRAM, real time clock, crystal, power-
fail control circuit and lithium energy source
Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
Century byte register
Totally nonvolatile with over 10 years of operation in
the absence of power
BCD coded century, year, month, date, day, hours,
minutes, and seconds with automatic leap year
compensation valid up to the year 2100
Battery voltage level indicator flag
Power-fail write protection allows for ±10% VCC
power supply tolerance
Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
DIP Module only
– Standard JEDEC bytewide 8k x 8 static RAM
pinout
PowerCap Module Board only
– Surface mountable package for direct connection
to PowerCap containing battery and crystal
– Replaceable battery (PowerCap)
– Power-On Reset Output
– Pin for pin compatible with other densities of
DS174XP Timekeeping RAM
ORDERING INFORMATION
DS1743P-XXX (5V)
-70 70 ns access
-100 100 ns access
blank 28-pin DIP Module
P 34-pin PowerCap Module
board*
*DS1743WP-XXX
(3.3V)
-120 120 ns access
-150 150 ns access
blank 28-pin DIP Module
P 34-pin PowerCap Module
board*
*DS9034PCX (PowerCap) Required:
(must be ordered separately)
PIN ASSIGNMENT
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CE2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
28-Pin Encapsulated Package
(700-mil Extended)
NC
NC
NC
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1 34
2 33
3 32
4 31
5 30
6 29
7 28
8 27
9 26
10 25
11 24
12 23
13 22
14 21
15
16
X1 GND VBAT X2
20
19
17 18
34-Pin Powercap Module Board
(Uses DS9034PCX Powercap)
NC
NC
NC
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PIN DESCRIPTION
A0-A12
- Address Input
CE - Chip Enable
CE2 - Chip Enable 2 (DIP
Module only)
OE - Output Enable
WE - Write Enable
VCC
GND
- Power Supply Input
- Ground
DQ0-DQ7 - Data Input/Output
NC - No Connection
RST - Power-On Reset Output
(PowerCap Module board only)
X1, X2
- Crystal Connection
VBAT
- Battery Connection
1 of 17
022301
1 page  
DS1743/DS1743P
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , on CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power fail point, VPF, (point at which write protection occurs) the internal
clock registers and SRAM are blocked from any access. At this time(PowerCap only)the power fail reset
output signal ( RST ) is driven active and will remain active until VCC returns to nominal levels. When VCC
falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to
nominal levels. The 3.3-volt device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
time the power fail reset output signal ( RST ) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than Vso, the device power is switched from VCC to the backup supply (VBAT)
when VCC drops below VPF. If VPF is greater than Vso, the device power is switched from VCC to the backup
supply (VBAT) when VCC drops below Vso. RTC operation and SRAM data are maintained from the battery
until VCC is returned to nominal levels. The RST (PowerCap only) signal is an open drain output and
requires a pull up. Except for the RST , all control, data, and address signals must be powered down when
VCC is powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the VCC supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC and RAM are questionable.
5 of 17
5 Page 
DS1743/DS1743P
POWER-UP/DOWN CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH , CE2 at VIL,
Before Power-Down
tPD 0
VCC Fall Time: VPF(MAX) to
VPF(Min)
tF 300
VCC Fall Time: VPF(MIN) to VSO
tFB
10
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tR 0
Power-up Recover Time
tREC
Expected Data Retention Time
(Oscillator On)
tDR 10
µs
µs
µs
µs
35 ms
years
6, 7
POWER-UP/POWER-DOWN TIMING 5-VOLT DEVICE
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS1743.PDF ] | |
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