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ST10F166 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST10F166
Beschreibung 16-BIT MCU WITH 256K BYTE FLASH MEMORY
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
ST10F166 Datasheet, Funktion
ST10F166
16-BIT MCU WITH 256K FLASH MEMORY
s High Performance 16-bit CPU with 4-Stage
Pipeline
s 100 ns Instruction Cycle Time at 20 MHz CPU
Clock
s 500 ns Multiplication (16 × 16 bit), 1 µs Division
(32 / 16 bit)
s Enhanced Boolean Bit Manipulation Facilities
s Register-Based Design with Multiple Variable
Register Banks
s Single-Cycle Context Switching Support
s Up to 256 KBytes Linear Address Space for
Code and Data
s 1 KByte On-Chip RAM
s 32 KBytes On-Chip Flash EPROM with Bank
Erase Feature
s Protection-Optional Flash Memory
s Dedicated Flash Control Register with
Operation Lock Mechanism
s 12 V External Flash Programming Voltage
s Flash Program Verify and Erase Verify Modes
s 1000 Flash Program/Erase Cycles guaranteed
s Programmable External Bus Characteristics for
Different Address Ranges
s 8-Bit or 16-Bit External Data Bus
s Multiplexed or Demultiplexed External Address/
Data Buses
s Hold and Hold-Acknowledge Bus Arbitration
Support
s 512 Bytes On-Chip Special Function Register
Area
s Idle and Power Down Modes
s 8-Channel Interrupt-Driven Single-Cycle Data
Transfer Facilities via Peripheral Event
Controller (PEC)
PQFP100
s 16-Priority-Level Interrupt System
s 10-Channel 10-bit A/D Converter with 9.7 µs
Conversion Time (ST10F166)
s 16-Channel Capture/Compare Unit
s Two Multi-Functional General Purpose Timer
Units with 5 Timers
s Two Serial Channels (USARTs)
s Programmable Watchdog Timer
s Up to 76 General Purpose I/O Lines
s Supported by a Wealth of Development Tools
like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers,
Programming Boards
s On-Chip Bootstrap Loader
s 100-Pin Plastic PQFP Package
February 1996
This is preliminary information from SGS-THOMSON. Details are subject to change without notice.
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ST10F166 Datasheet, Funktion
ST10F166
Table 1. Pin Definition and Function
Symbol
NMI
Pin
Number
29
Input (I)
Output (O)
I
Function
Non-Maskable Interrupt Input. A high to low transition at this pin
causes the CPU to vector to the NMI trap routine. When the
PWRDN (power down) instruction is executed, the NMI pin must
be low in order to force the ST10R165 to go into power down
mode. If NMI is high, when PWRDN is executed, the part will con-
tinue to run in normal mode.
If not used, pull NMI high externally.
Address Latch Enable Output. Can be used for latching the ad-
ALE 25 O dress into external memory or an address latch in the multiplexed
bus modes.
RD
26
O
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
P1.0 –
P1.15
30 - 37
40 - 47
I/O
the output driver is put into high-impedance state. Port 1 is used
as the 16-bit address bus (A) in demultiplexed bus modes and
also after switching from a demultiplexed bus mode to a multi-
plexed bus mode..
Port 5 is a 10-bit input-only port with Schmitt-Trigger characteris-
P5.0 –
48 – 53
I
tics. The pins of Port 5 also serve as the (up to 10) analog input
P5.9
56 – 59 I channels for the A/D converter, where P5.x equals ANx (Analog
input channel x) for ST10F166 & ST10F166-16.
62 – 77 I/O Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The following Port 2 pins also serve for alternate functions:
P2.0 –
62
I/O P2.0CC0IOCAPCOM: CC0 Cap.-In/Comp.Out
... ... ...
P2.15
...
75
I/O P2.13CC13IOCAPCOM: CC13 Cap.-In/Comp.Out,
O BREQExternal Bus Request Output
76
I/O P2.14CC14IOCAPCOM: CC14 Cap.-In/Comp.Out,
O HLDAExternal Bus Hold Acknowl. Output
77
I/O P2.15CC15IOCAPCOM: CC15 Cap.-In/Comp.Out,
I HOLDExternal Bus Hold Request Input
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6 Page









ST10F166 pdf, datenblatt
ST10F166
5 FLASH MEMORY PROGRAMMING AND ERASURE
The FLASH memory is programmed using the PRESTO F Program Write algorithm for
reliability. This algorithm provides a typical programming time of 25µs per word and
erasing of 1s per bank.
Erasure of the FLASH memory is performed in the program mode using the PRESTO
F Erase algo-rithm, and operates on the selected bank of the memory.
Timing of the Write/Erase cycles is automatically generated by a programmable timer
and completion is indicated by a flag. A second flag indicates that the VPP voltage was
correct for the whole programming cycle to ensure reliability.
The FLASH memory features a typical endurance of 100 Erase/Program cycles.
6 FLASH MEMORY SECURITY
Security and reliability are enhanced by the built-in features. A key code sequence is
used to enter the Write/Erase mode preventing false write cycles, while a program-
mable option (set by the programming board) prevent any access to the FLASH
memory from the internal RAM or from External Memory. If the security option is set,
the FLASH memory is accessed only from program within the FLASH memory area.
This protection may be disabled by instructions executed from the FLASH memory
only (when not in write/erase mode).
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