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PDF TA0038 Data sheet ( Hoja de datos )
| Número de pieza | TA0038 | |
| Descripción | DC ACCURATE FSK MODULATOR | |
| Fabricantes | RF | |
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TA0038
DC Accurate FSK Modulator
TA0038
A typical, low cost, FSK modulator is implemented by
injecting the modulation voltage into the phase lock
loop of the carrier synthesizer. This is done in two
ways, by summing the modulation voltage and the loop
error voltage together and applying that to a VCO tun-
ing port. Or, by using a separate tuning port usually
having lower sensitivity to voltage changes. The modu-
lating data would change the carrier frequency by a
predetermined amount (deviation). This, however,
causes a frequency error within the PLL that the loop
begins to correct for. The effect of the loop correcting
for the frequency errors caused by the modulation is
analogous to passing the modulating signal through a
high pass filter. Lower frequency components of the
modulation signal get filtered off (or even eliminated).
This results in unreliable communications for random
data streams, especially for long strings of non-chang-
ing bits.
There have been several solutions developed and
implemented that address this problem. One approach
is to predistort the modulation signal to compensate for
the effects of the PLL. This has limited results and a
finite frequency range. Another commonly used
method is to encode the data stream with such tech-
niques as Manchester coding or split phase coding.
The basis of this coding is to send two complementary
symbols for every data bit, thus a transition is guaran-
teed for every data bit. This is very effective in that it
fixes the lowest frequency component of the modula-
tion signal so that a loop bandwidth can be designed to
have a minimal effect on the coded data. Unfortunately,
this means that the effective data rate of the radio is
doubled, increasing channel bandwidth. The encoding
procedure is rather simple (exclusive OR the data and
clock together). The decoding is much more compli-
cated requiring some synchronization to guarantee the
correct two symbols are used to decode the data bit.
Other approaches avoid the problem altogether by
modulating outside of the PLL loop. Modulating the ref-
erence crystal, for example, can do this. A varactor can
be used with a crystal to pull the center frequency to
the mark and space frequencies. Since the modulation
occurs outside the loop, the PLL does not effect the
modulation signal, it simply tracks the changes in the
reference frequency. The pullability of the crystal will
limit the achievable frequency deviation and thus the
maximum data rate using this method. Given the vari-
ances in crystals and varactors, this would require tun-
ing to set the desired deviation. Another method would
be to generate the reference frequency with a Direct
Digital Synthesizer and modulate within this synthe-
sizer. This works very well and accurately but cost is
considerably higher.
Another type of approach is to program the mark and
space frequencies in the PLL. There are several ways
to do this depending on the programmability of the PLL
divider registers. A new technique takes advantage of
low cost ICs that contain an integrated, simple PLL and
the VCO functions. These devices are typically
designed to be multipliers of a reference crystal to gen-
erate a local oscillator frequency or they can be modu-
lated for FSK transmitters. One component of the PLL
is the prescaler. This divides the VCO frequency down
to the reference crystal frequency. The prescaler usu-
ally has 2 divide-by rates (N and N+1) and is referred
to as dual modulus. By controlling the ratio of the 2
rates, the VCO frequency can be set to a desired fre-
quency. Using one ratio for logic 1 and another ratio for
logic 0 can effectively generate FSK modulation that is
not affected by the PLL and therefore can be used for
signals that contain near DC components.
One way to generate this ratio is to use a pulse width
modulator. This is similar to how a typical PLL would
work. The prescaler would divide by N for part of a
cycle and then divide by N+1 for the remainder. This
would synthesize a frequency that is N+(duty cycle)
times the reference frequency. The step size between
two frequencies is set by the resolution of the counter
used to set the duty cycle. Another way to generate a
ratio is to start with a clock pattern and periodically
inject an extra bit. The ratio is then tied to the period of
the injected bit. By changing the period of the injected
bit, a new ratio is formed and thus a new synthesized
frequency.
An example of this approach is as follows using a 4-bit
programmable counter. By loading one set of bits into
the counter with the carry-out, the counter can be pro-
grammed to divide the clock by s, (Fclk/s), resulting in
a cycle rate of s/Fclk second. The first divider output,
Qa, normally looks like Fclk divided by 2. If the pro-
grammed value s is chosen such that a “1” is loaded
into the “a” divider (an odd number), then the Qa out-
put stays a “1” from the previous state. This puts one
more “1” in the Qa output than “0” for every cycle of the
counter. This unequal number of 1s and 0s will define a
Copyright 1997-2000 RF Micro Devices, Inc.
13-187
13
1 page  
TA0038
Figure 6. Linear Final Stage RMS Collector Currents for the Two Cases as the Input Signal is Varied
Figure 7. RF2510 Spurious Output with Modulation
Copyright 1997-2000 RF Micro Devices, Inc.
13
13-191
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet TA0038.PDF ] | |
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