Datenblatt-pdf.com


ZL30106 Schematic ( PDF Datasheet ) - Zarlink

Teilenummer ZL30106
Beschreibung SONET/SDH/PDH Network Interface DPLL
Hersteller Zarlink
Logo Zarlink Logo 




Gesamt 48 Seiten
ZL30106 Datasheet, Funktion
ZL30106
SONET/SDH/PDH
Network Interface DPLL
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between inputs and outputs
• Supports output wander and jitter generation
specifications for SONET/SDH and PDH
interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs:
- 2.048 MHz (E1), 16.384 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
- 19.44 MHz (SONET/SDH)
- 1.544 MHz (DS1) and 3.088 MHz
- a choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Provides automatic entry into Holdover and return
from Holdover
• Manual and automatic hitless reference switching
• Provides lock, holdover and accurate reference
fail indication
October 2004
Ordering Information
ZL30106QDG 64 pin TQFP
-40°C to +85°C
• Selectable loop filter bandwidth of 29 Hz or
922 Hz
• Less than 24 psrms intrinsic jitter on the
19.44 MHz output clock, compliant with GR-253-
CORE OC-3 and G.813 STM-1 specifications
• Less than 0.6 nspp intrinsic jitter on all PDH output
clocks and frame pulses
• Selectable external master clock source: clock
oscillator or crystal
• Simple hardware control interface
Applications
• Line card synchronization for SONET/SDH and
PDH systems
• Wireless base-station Network Interface Card
• AdvancedTCA™ and H.110 line cards
OSCi OSCo TIE_CLR
BW_SEL LOCK
OUT_SEL2
REF0
REF_SYNC0
REF1
REF_SYNC1
REF2
REF_FAIL0
REF_FAIL1
REF_FAIL2
APP_SEL1:0
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0 HMS
HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.






ZL30106 Datasheet, Funktion
ZL30106
Data Sheet
1.0 Change Summary
Changes from June 2004 Issue to October 2004 Issue. Page, section, figure and table numbers refer to this issue.
Page
1
7
18
33
34
34
37
38
42
Item
Text
Figure 2
Section 3.3
Section 6.4
Table “Absolute Maximum Ratings*“
Table “DC Electrical Characteristics*“
Table “AC Electrical Characteristics* -
Input to output timing for REF0, REF1
and REF2 references when
TIE_CLR = 0 (see Figure 24).“
Section 7.1
Section 7.2
Change
Jitter changed to 24 ps from 20 ps
Added note specifying not e-Pad
Changed 200 ns to 20 ns in "HMS=0" section
Corrected time-constant of example reset circuit
Corrected package power rating
Corrected current consumption
Corrected Schmitt trigger Vt- levels
Corrected output voltage note to reflect two pad strengths
Updated Min. Max. values
Corrected pulse widths
Changed jitter numbers
6
Zarlink Semiconductor Inc.

6 Page









ZL30106 pdf, datenblatt
ZL30106
Data Sheet
3.0 Functional Description
The ZL30106 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame)
signals to SONET/SDH and PDH network interface cards. The ZL30106 supports the following applications:
• DS1/E1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
• Derived DS1 compliant with ITU-T G.783
• DS2/DS3/E2/E3 compliant with ANSI T1.102 and ITU-T G.823
• SONET/SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Figure 1 is a functional block diagram which is described in the following sections.
3.1 Reference Select Multiplexer (MUX)
The ZL30106 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal, is selected
as input to the TIE Corrector Circuit based on the reference selection (REF_SEL1:0) inputs. REF0 and REF1 can
be accompanied by a 2 kHz or 8 kHz frame pulse on the REF_SYNC0 and REF_SYNC1 inputs. Input REF_SYNC0
is always associated with input REF0 while input REF_SYNC1 is always associated with input REF1.
The use of the combined REF and REF_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF_SYNC input. This feature supports the
implementation of line card clocks where the line card locks to the backplane clock with a filter suitable for good
tracking (high bandwidth) yet still provides a (multi) frame locked to the backplane (multi) frame.
3.2 Reference Monitor
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this
information to the various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the selected accuracy range, see Table 1.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
12
Zarlink Semiconductor Inc.

12 Page





SeitenGesamt 48 Seiten
PDF Download[ ZL30106 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ZL30100T1/E1 System SynchronizerZarlink Semiconductor Inc
Zarlink Semiconductor Inc
ZL30101T1/E1 Stratum 3 System SynchronizerZarlink Semiconductor Inc
Zarlink Semiconductor Inc
ZL30102T1/E1 Stratum 4/4E Redundant System Clock SynchronizerZarlink Semiconductor
Zarlink Semiconductor
ZL30105T1/E1/SDH Stratum 3 Redundant System Clock SynchronizerZarlink Semiconductor
Zarlink Semiconductor
ZL30106SONET/SDH/PDH Network Interface DPLLZarlink
Zarlink

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche