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ST62T40B Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer ST62T40B
Beschreibung 8-BIT OTP/EPROM MCU WITH LCD DRIVER / EEPROM AND A/D CONVERTER
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
ST62T40B Datasheet, Funktion
ST62T40B/E40B
8-BIT OTP/EPROM MCU WITH LCD DRIVER,
EEPROM AND A/D CONVERTER
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +85°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 24 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
– LCD segments (8 combiport lines)
s 4 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s Two 8-bit Timer/Counter with 7-bit
programmable prescaler
s Digital Watchdog
s 8-bit A/D Converter with 12 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s LCD driver with 45 segment outputs, 4
backplane outputs and selectable multiplexing
ratio.
s 32kHz oscillator for stand-by LCD operation
s Power Supply Supervisor (PSS)
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s One external Non-Maskable Interrupt
s ST6240-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T40B
ST62E40B
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
16 to 24
16 to 24
August 1999
PQFP80
CQFP80W
(See end of Datasheet for Ordering Information)
Rev. 2.6
1/72
1






ST62T40B Datasheet, Funktion
ST62T40B/E40B
INTRODUCTION (Cont’d)
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
fined in the programmable option byte of the
OTP/EPROM versions.OTP devices offer all the
advantages of user programmability at low cost,
which make them the ideal choice in a wide range
of applications where frequent code changes, mul-
tiple code versions or last minute programmability
are required.
These compact low-cost devices feature two Tim-
ers comprising an 8-bit counter and a 7-bit pro-
grammable prescaler, EEPROM data capability, a
serial synchronous port interface (SPI), an 8-bit
A/D Converter with 12 analog inputs, a Digital
Watchdog timer, and a complete LCD controller
driver, making them well suited for a wide range of
automotive, appliance and industrial applications.
Table 1. ST6240 Pin Description
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
name
S43
S44
S45
S46
S47
S48
COM4
COM3
COM2
COM1
VLCD1/ 3
VLCD2/ 3
VLCD
PA7/ Ain
PA6/ Ain
PA5/ Ain
PA4/ Ain
TEST
PA3/ Ain
PA2/ Ain
PA1/ Ain
PA0/ Ain
VDD
VSS
Pin
number
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin
name
RESET
OSCout
OSCin
WDON
NMI
TIMER
PB7/ Sout *
PB6/ Sin*
PB5/ SCL *
PB4 *
PB3/ Ain
PB2/ Ain
PB1/ Ain
PB0/ Ain
OSC32out
OSC32in
*Note: 20mA Sink
Figure 2. 80 Pin QFP Package
80
1
2
3
65
64
24
25
41
40 VR01649A
Pin
number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin
name
PSS
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
Pin
number
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin
name
S27
S28
S29
S30
S31
S32
PC0/S33
PC1/S34
PC2/S35
PC3/S36
PC4/S37
PC5/S38
PC6/S39
PC7/S40
S41
S42
6/72
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6 Page









ST62T40B pdf, datenblatt
ST62T40B/E40B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM
(DRBR)
Address: CBh — Write only
Bank
Register
70
- - - DRBR4 DRBR3 - DRBR1 DRBR0
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3 - DRBR3. This bit, when set, selects RAM
Page 1.
Bit2. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR regis-
ter) located at address CBh of the Data Space ac-
cording to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address CBh; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The number of banks has to be load-
ed in the DRBR register and the instruction has to
point to the selected location as if it was in bank 0
(from 00h address to 3Fh address).
This register is not cleared during the MCU initiali-
zation, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional informa-
tion. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes :
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupt service routine, as the service routine can-
not save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Other-
wise two or more pages are enabled in parallel,
producing errors.
Table 6. Data RAM Bank Register Set-up
DRBR
00h
01h
02h
08h
10h
other
ST62T40B/E40B
None
EEPROM Page 0
EEPROM Page 1
RAM Page 1
RAM Page 2
Reserved
12/72
12

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